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Display driver circuit

一种显示驱动、电路的技术，应用在峰值电流抑制领域，能够解决误动作等问题，达到消除误动作、抑制电源电压的变动、峰值电流减小的效果

Active Publication Date: 2007-01-31
LAPIS SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, there is a risk of malfunction

Method used

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Examples

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Embodiment 1

[0021] figure 1 It is a configuration diagram showing the display drive circuit of the first embodiment of the present invention.

[0022] The display drive circuit is a display drive circuit that drives a fluorescent display tube or a liquid crystal display, and has a holding circuit (for example, a data latch) 11, and takes in n display data D1, D2, and D2 provided in parallel in accordance with a latch signal LAT. ..Dn. When the latch signal LAT is'H', the data latch 11 fetches and outputs the display data D1 to Dn in parallel. When the latch signal LAT is'L', it keeps the data fetched during the'H' period as it is. Signal, and continue to output.

[0023] The output side of the data latch 11 and the AND gate 12 gated by the common blank signal / BLK 1 , 12 2 ,...12 n connection. That is, AND gate 12 1 ~12 n When the blank signal / BLK is'L', regardless of the output of the data latch 11, always output'L'. When the blank signal / BLK is'H', the output signal of the data latch 11...

Embodiment 2

[0042] Figure 4 It is a structural diagram showing a display drive circuit of the second embodiment of the present invention. Right and figure 1 The same elements in the elements are given the same symbols.

[0043] The display drive circuit is removed figure 1 Delay circuit in 13 1 ~13 n , Make AND gate 12 1 ~12 n Output side and driver 14 1 ~14 n At the same time, the delay buffer 15 with the same structure as the cascade connection circuit is used. 1 , 15 2 ,...15 n-1 The delay circuit is constructed so that the AND gate 12 1 ~12 n The blank signal / BLK is delayed in sequence. That is, for AND gate 12 1 Apply blank signal / BLK. To AND gate 12 2 Apply using delay buffer 15 1 Delay the blank signal / BLK signal after time τ. To AND gate 12 3 Apply using delay buffer 15 1 And 15 2 Delay the blank signal / BLK signal after the time 2τ. The following is the same, for the final AND gate 12 n Apply using delay buffer 15 1 ~15 n-1 Delay the blank signal / BLK by a time (n-1)τ. The rest of...

Embodiment 3

[0056] Figure 5 It is a diagram showing the structure of a delay buffer according to the third embodiment of the present invention.

[0057] The delay buffer is to replace image 3 Delay buffer 15 1 ~15 n-1 The circuit set up is basically a cascade-connected circuit with two-stage inverters. The front-stage inverter connects two inverters in parallel, and uses a control signal to separate one of the inverters, thereby controlling the delay time.

[0058]That is, the delay buffer has a first CMOS inverter composed of PMOS (P-channel MOS transistors) 21 and 22 connected in series between the power supply potential VDD and the node N1, and connected in series between the node N1 and the ground. NMOS (N-channel MOS transistors) 23 and 24 are formed between the potential GND. The control signal CON and the control signal / CON in which the control signal CON is inverted by the inverter 25 are respectively applied to the gates of the NMOS 24 and PMOS 21 for switching. In addition, a del...

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Abstract

The aim of the invention is to suppress the peak current of a display drive circuit having a blank control function. Pieces of display data (D1-Dn) are latched by a data latch (11) and provided to AND gates (121-12n) to which gate control is performed by a blank signal / BLK. Output signals of the AND gates (121-12n) are provided to drivers (141-14n) after being delayed by delay circuits (131-13n) having mutually different delay time (tau 1-tau n) and supplied to a display unit as drive signals Q1-Qn. Since timing of change of signals S1-Sn provided to each of the drivers 141-14n is distributed by the delay circuits (131-13n), timing of current i 1-i n flowing to the drivers (141-14n) is also distributed and the total sum Sigma 1 of the current i 1-i n shows gently temporal change and a peak current value decreases.

Description

Technical field [0001] The present invention relates to a display driving circuit for driving a fluorescent display tube or a liquid crystal display, and more particularly to a peak current suppression technology in a display driving circuit with a blank control function. Background technique [0002] [Patent Document 1] JP 5-110266 A [0003] figure 2 It is a configuration diagram showing a conventional drive circuit described in Patent Document 1. [0004] The driving circuit is a circuit that lights up and drives LEDs (light emitting diodes) or fluorescent display tubes. Therefore, it consists of a 4-bit shift register 1, a 4-bit data latch 2, 4 AND (logical product) gates 3, FF (Flip-flop) 4 and output terminals Q0 ~ Q3 constitute. The shift register 1 is a circuit for serially inputting a data signal DATA in synchronization with a clock signal CLK and converting in parallel and outputting it as a 4-bit output signal. The data latch 2 is the following circuit: when the latc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/20G09G3/36G11C7/10H03K5/15
CPCG09G1/00G09G5/00G09G2330/025G09G2310/0275G09G3/20G09G3/30G09G3/32G09G3/36
Inventor 今吉崇博石政恒宇
Owner LAPIS SEMICON CO LTD
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