Memory device and dual port static RAM

Abstract

Disclosed is a memory device and dual port static RAM. The memory device comprises a memory cell arrays, at least two signal lines and a interleaving region. The memory cell arrays comprise a plurality of memorizers arranged in lines or in rows wherein each line or row is provided with several memorizers. The signal lines extend along one line of the memorizers, and are electrically connected with the first end and the second end of each memorizers. The interleaving region is associated with each line, and the second signal line in the first line crosses the first interleaving region. The memory device and dual port static RAM according to the invention can reduce the resistance difference and circuit area, improve the efficiency and mass production.

Description

technical field [0001] The present invention relates generally to semiconductor memory devices, and more particularly to memory devices and dual-port SRAMs with reduced resistance variation. Background technique [0002] The physical size of a feature on a semiconductor chip is generally referred to as the feature size. As long as the feature size is reduced or reduced, more elements or structures can be allowed to be placed on a single wafer, and more elements or structures can be allowed to be placed on a single wafer, thereby reducing the cost per die. round or production cost per wafer. Some semiconductor devices have memory cells, and feature sizes must be reduced to reduce production costs. In addition to reducing the feature size, the level of integration can be increased by changing the layout, allowing more units to be placed on each wafer. Similarly, there are many goals that can be achieved by changing the layout, for example, to improve the performance of the ...

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Problems solved by technology

Therefore, for cost considerations, a more aggressive layout is often required, but the impact on component performance must also be considered

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