Charge pump power supply

Abstract

The present invention discloses a charge pump based power supply for low voltage dynamic random access memory (DRAM), including a charge pump and a non-overlapping clock signal generator. The charge pump consists of a cascade of two pumps coupled in parallel. Each pump cascade consists of multiple pump stages connected in series between the supply voltage and the output node. Each cascaded adjacent stage is clocked at the opposite phase of the system clock signal. The charge pump drives the output node on the rising and falling edges of the system clock signal. The non-overlapping clock signal generator includes charge-sharing transistors controlled by equalization pulses generated by the outputs of latches that equalize the non-overlapping output clock signals by charge sharing during non-overlapping periods between system clock phases. The non-overlapping clock signal generator also includes transmission gates that ensure equalization of the non-overlapping cycles.

Description

[0001] This application claims priority to US Provisional Patent Application SC / Serial No. 60 / 252,219, filed November 21, 2000, and entitled "Charge Pump Based on Low Voltage DRAM Power Supplies." technical field [0002] The present invention relates to charge pumps for boosting supply voltages to obtain high voltages. In particular, the present invention relates to charge pumps based on power supplies for use with low voltage dynamic random access memory (DRAM). Background technique [0003] Voltage multipliers are commonly used to step up the voltage of a power supply to provide the high voltage required to operate circuit components. One type of voltage multiplier is called a charge pump and is commonly used in memory systems to provide the voltages needed to access, program or erase memory cells. [0004] For example, in the field of dynamic random access memory (DRAM), charge pump circuits are commonly used to generate the voltages that enable memory cells to access t...

AI Technical Summary

Problems solved by technology

The four-stage, four-phase charge pump also results in a larger circuit size and greater energy loss at the higher peak and average current levels required by DRAM

Therefore, there is an overlap of potentials in the operation of equalization transistor N1 and tri-state buffer transistors P1, N11 and P2, N12

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