Thin packing structure for enhancing crystal fin radiation

Abstract

The invention is concerned with the thin sealing structure for enhancing the radiation of the wafer back, including: the base panel, the wafer, and the sealing colloid; the base panel is with the upper surface, the under surface, and the transfixing geode; the wafer is contained at the geode of the base panel and with the initiative surface and the back surface, the initiative surface forms plural number of welding underlay and electric connects with the base panel, the back surface of the wafer forms plural number of the grooves; the sealing colloid forms on the upper surface of the base panel, covers the initiative surface of the wafer, and show the back surface and the grooves of the wafer, therefore the grooves is with the effects to enhance the radiation of the wafer back and intensity of the wafer.

Description

technical field [0001] The invention relates to an integrated circuit package structure with an exposed crystal back, in particular to a thin package structure which improves heat dissipation of the crystal back. Background technique [0002] As the packaging technology of integrated circuits becomes lighter, thinner, shorter, and smaller, the demand for heat dissipation is getting higher and higher. Generally, a heat sink is added to the packaging structure to improve the heat dissipation of the packaging structure, but it will increase the heat dissipation of the packaging structure. Therefore, considering the total thickness of the package, a package structure that directly exposes the back of the chip to improve heat dissipation has been developed. As disclosed in US Pat. No. 5,696,666, please refer to FIG. 1, which is a schematic cross-sectional view of a conventional ball grid array package structure with an exposed crystal back. The conventional integrated circuit pac...

AI Technical Summary

Problems solved by technology

A sealant 30 is to seal the active surface 11 of the chip 10 and the upper surface 22 of the substrate 20, but the back side 12 of the chip 10 is directly exposed to the lower surface 23 of the substrate 20, so that the heat generated by the chip 10 during operation , through the back side 12 to directly dissipate heat, but the known heat dissipation efficiency of the chip 10 is related to the exposed surface area of ​​the chip back side 12, and the maximum surface area exposed on the chip back side in the existing conventional packaging structure is only the size of the chip, It cannot be increased, so the maximum heat

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