Display apparatus and driving method thereof

[0068] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. First, a typical reference implementation of an image display device using the principle of the present invention will be explained with reference to FIG. 1. As shown in the figure, the active matrix display device includes a pixel array unit 1 serving as a main component and its peripheral circuits. The peripheral circuit includes a horizontal selector 3, a write scanner 4, a drive scanner 5, a first compensation scanner 71, and a second compensation scanner 72. The pixel array unit 1 has pixel circuits 2 arranged to form a matrix. Each pixel circuit 2 is disposed at the intersection of the scan line WS positioned in the row direction of the matrix and the data signal line SL positioned in the column direction of the matrix. In order to make the figure easy to understand, only one pixel circuit 2 is shown in an enlarged form. The horizontal selector 3 drives the data signal line SL. The horizontal selector 3 is a unit for supplying a video signal to the data signal line SL. The write scanner 4 drives the first scan line WS. It should be noted that in addition to the first scan line WS, scan lines DS, AZ1, and AZ2 parallel to the first scan line WS are also provided. The drive scanner 5, the first compensation scanner 71, and the second compensation scanner 72 drive the second scan line DS, the scan line AZ1, and the scan line AZ2, respectively. The write scanner 4, the drive scanner 5, the first compensation scanner 71, and the second compensation scanner 72 constitute a scanner unit that sequentially scans each row of the pixel array in each horizontal scanning period. When the pixel circuit 2 is selected by the first scan line WS, the pixel circuit 2 samples the video signal provided by the data signal line SL. When the pixel circuit 2 is selected by the second scan line DS, the light emitting device EL in the pixel circuit 2 is driven in accordance with the sampled video signal. When the pixel circuit 2 is selected by the scan lines AZ1 and AZ2, the pixel circuit 2 performs a predetermined compensation operation.

[0069] The pixel circuit 2 has five thin film transistors, that is, the transistors Tr1 to Tr4 and the transistor Trd, the capacitive element (or pixel capacitor) Cs, and the light emitting device EL as described above. Each of the transistors Tr1 to Tr3 and the transistor Trd is an N-channel polysilicon TFT (thin film transistor). Meanwhile, the switching transistor Tr4 is a P-channel polysilicon TFT. The capacitive element Cs forms a capacitor unit of the pixel circuit 2. The light emitting device EL is generally an organic EL device designed in the form of a diode having an anode and a cathode. However, it is not intended to limit the scope of the present invention to the structural form of the pixel circuit 2 described above. In addition, the light emitting device EL may generally be any device that emits light by current driving.

[0070] The driving transistor Trd, which is an important device of the pixel circuit 2, has a gate G connected to one end of the pixel capacitor Cs and a source S connected to the other end of the pixel capacitor Cs. The gate G of the driving transistor Trd is also connected to another reference potential Vss1 via the switching transistor Tr2. The drain of the driving transistor Trd is connected to the power supply Vcc via the switching transistor Tr4. The gate of the switching transistor Tr2 is connected to the scan line AZ1, and the gate of the switching transistor Tr4 is connected to the second scan line DS. The anode of the light emitting device EL is connected to the source S of the driving transistor Trd, and the cathode of the light emitting device EL is grounded. In some cases, the ground potential is called Vcath. The source S of the driving transistor Trd is connected to a predetermined reference potential Vss2 via the switching transistor Tr3. The gate of the switching transistor Tr3 is connected to the scanning line AZ2. The sampling transistor Tr1 is provided between the data signal line SL and the gate G of the driving transistor Trd. The gate of the sampling transistor Tr1 is connected to the first scan line WS.

[0071] In the structure as described above, the first control signal WS provided by the first scan line WS in a predetermined sampling period causes the sampling transistor Tr1 to enter the conductive state, and the video signal Vsig provided by the data signal line SL is sampled and combined The sampled video signal Vsig is stored in the pixel capacitor Cs. In accordance with the sampled video signal Vsig, the pixel capacitor Cs applies the input voltage Vgs between the gate G and the source S of the driving transistor Trd. During a predetermined light emitting period, the driving transistor Trd provides the light emitting device EL with an output current (or leakage current) Ids according to the input voltage Vgs. It should be noted that the output current Ids generated by the drive transistor Trd exhibits a characteristic dependent on the carrier mobility μ in the channel region of the drive transistor Trd and the threshold voltage Vth of the drive transistor Trd. The output current Ids generated by the driving transistor Trd causes the light emitting device EL to emit a light beam representing the brightness of the video signal Vsig.

[0072] A typical reference implementation of the original image display device of the present invention is characterized in that the pixel circuit 2 adopts a compensation unit including switching transistors Tr2 to Tr4. In order to zero the influence of the dependency of the output current Ids on the carrier mobility μ in the channel region of the drive transistor Trd, the input voltage Vgs stored in the pixel capacitor Cs is compensated in advance at the beginning of the light emission period. More specifically, according to the control signals WS and DS provided by the scanning lines WS and DS, respectively, the compensation unit including the switching transistors Tr2 to Tr4 operates during a part of the sampling period to draw the output current from the driving transistor Trd having the sampled video signal Vsig Ids and the extracted output current Ids are fed back to the pixel capacitor Cs in a negative feedback manner, thereby compensating for the influence of the dependence of the output current Ids on the mobility μ of the carriers. In addition, in order to zero the influence of the output current Ids and the threshold voltage of the drive transistor Trd, the threshold voltage Vth is detected before the sampling period, and the detected threshold voltage Vth is added to the input voltage Vgs.

[0073] In the case of a typical reference embodiment of an image display apparatus, the driving transistor Trd is an N-channel transistor, the drain and source S of which are connected to the power supply Vcc and the light emitting device EL, respectively. In this case, at the beginning of the light-emitting period, the light-emitting period overlaps with the latter part of the sampling period before the light-emitting period, and the compensation unit described above extracts the output current Ids from the drive transistor Trd, and extracts the output current Ids from the driving transistor Trd. The output current Ids is fed back to the pixel capacitor Cs in a negative feedback manner. At the beginning of the light-emitting period, the compensation unit also operates to draw the output current Ids from the source S of the drive transistor Trd and add the drawn output current Ids to the capacitance element of the light-emitting device EL. Specifically, the light emitting device EL is a light emitting device designed in the form of a diode having an anode connected to the source S of the driving transistor Trd and a cathode connected to the ground. In this structure, the compensation unit including the switching transistors Tr2 to Tr4 preliminarily places the anode and cathode of the diode-type light-emitting device in a reverse bias state, so that when the output current Ids drawn from the source S of the driving transistor Trd flows into the light-emitting In the case of the device EL, the light-emitting device EL is used as a capacitance element of the capacitance element described above. It should be noted that the compensation unit can adjust the width t of the sub-period included in the latter part of the sampling period as a sub-period in which the output current Ids is drawn from the source S of the driving transistor Trd. Therefore, it is possible to optimize the amount of output current Ids fed back to the pixel capacitor Cs in a negative feedback manner.

[0074]Fig. 2 is a diagram showing a pixel circuit 2 cited in the image display device shown in Fig. 1. In order to make the model easy to understand, the video signal Vsig sampled by the sampling transistor Tr1, the input voltage Vgs applied to the driving transistor Trd, the output current I ds generated by the driving transistor Trd, and the capacitive element Coled of the light emitting device EL are additionally shown. The operation performed by the pixel circuit 2 of the typical reference embodiment applied to the image display device is explained with reference to FIG. 2 as follows.

[0075] FIG. 3 shows a timing chart of the pixel circuit 2 shown in FIG. 2. The operation performed by the pixel circuit 2 shown in FIG. 2 applied to a typical reference embodiment of an image display device is explained in more detail with reference to the timing chart in FIG. 3 as follows. FIG. 3 shows a waveform diagram of the control signals provided by the scan lines WS, AZ1, AZ2, and DS along the time axis T. In order to simplify the figure, every detail of the control signal is indicated by the symbol indicating the scan line that transmits the special control signal. Because each of the transistors Tr1, Tr2, and Tr3 is an N-channel transistor, each of the control signals transmitted by the scan lines WS, AZ1, and AZ2 is an active-high signal, which is set to High level and set to low level to invalidate the signal. On the other hand, because the switching transistor Tr4 is a P-channel transistor, the control signal transmitted by the second scanning line DS is an active-low signal, which is set to a low level in the active state and is set to invalidate the signal It is high level. It should be noted that FIG. 3 not only shows a timing chart of the waveforms of the control signals provided by the scan lines WS, AZ1, and AZ2, but also shows the timing of the voltage waveforms appearing at the gate G and the source S of the driving transistor Trd. Figure.

[0076] In the timing chart shown in FIG. 3, the period between timings T1 and T8 is one field (1f). During the 1f period, the pixel rows are sequentially scanned once. The timing chart shows the waveforms of the control signals WS, AZ1, AZ2, and DS applied to the pixels of each row.

[0077] At the timing T0 before the start of the field, all the control signals WS, AZ1, AZ2, and DS are set to low level. Therefore, the N-channel transistors Tr1, Tr2, and Tr3 are in an off state. In contrast, only the P-channel transistor Tr4 is in the on state. Thus, because the drive transistor Trd is connected to the power source Vcc via the transistor Tr4 in the on state, the drive transistor Trd will apply the output current Ids to the light emitting device EL according to the predetermined input voltage Vgs. As a result, at timing T0, the light emitting device EL emits a light beam. The input voltage Vgs applied to the driving transistor Trd is represented by the difference between the gate G and the source S of the driving transistor Trd.

[0078] At the timing T1 at the beginning of the field, the second control signal DS rises from a low level to a high level, causing the switching transistor Tr4 to be in an off state, and thus, the driving transistor Trd is disconnected from the power supply Vcc. Therefore, the light emission is terminated, and the non-light emission period begins. As a result, at the timing T1, all the transistors Tr1 to Tr4 are in the off state.

[0079] Subsequently, at timing T2, the control signals AZ1 and AZ2 rise from the low level to the high level, so that the switching transistors Tr2 and Tr3 are in the on state. As a result, the gate G of the drive transistor Trd is connected to the reference potential Vss1, and the source S of the drive transistor Trd is connected to the reference potential Vss2. The relationship (Vss1-Vss2)>Vth holds. Since Vgs>Vth, the potential difference (Vss1-Vss2) is applied to the gate G of the driving transistor Trd. Therefore, it is prepared to perform the threshold voltage compensation operation at timing T3. In other words, the period from the timing T2 to the time T3 corresponds to the reset period of the drive transistor Trd. In addition, the reference potential Vss2 is set to satisfy the relationship VthEL>Vss2, where the symbol VthEL represents the threshold voltage of the light emitting device EL. Therefore, a negative bias voltage is applied to the light emitting device EL, so that the light emitting device EL is in a so-called reverse bias state. In order to normally realize the threshold voltage compensation operation and the subsequent mobility compensation operation, a reverse bias state is required.

[0080] At timing T3, the control signal AZ2 is pulled down to a low level to be immediately followed by the second control signal DS. Thus, the switching transistor T3 enters the off state, but the switching transistor T4 enters the on state. As a result, the output current Ids flows into the pixel capacitor Cs, and the threshold voltage compensation operation is started. At that time, the gate G of the drive transistor Trd is maintained at the reference potential Vss1 so that the output current flows until the drive transistor Trd is turned off. When the driving transistor Trd is turned off, the potential appearing on the source S of the driving transistor Trd is equal to the difference (Vss1-Vth). At timing T4 after the operation of turning off the leakage current, the second control signal DS is set back to a high level, so that the switching transistor T4 enters the off state. In addition, the control signal AZ1 also transitions to a low level, so that the switching transistor Tr2 also enters the off state. As a result, the threshold voltage Vth, which is a fixed voltage, is stored at the pixel capacitor Cs. Therefore, the period from the timing T3 to the timing T4 is a period for detecting the threshold voltage Vth. For this reason, the period from timing T3 to timing T4 is called a threshold voltage compensation period.

[0081] At the timing T5 after the threshold voltage compensation operation as described above is performed, the first control signal WS is changed to a high level in order to turn on the sampling transistor Tr1. Thus, the video signal Vsig is stored in the pixel capacitor Cs. Compared with the equivalent capacitance Coled of the light emitting device EL, the capacitance of the pixel capacitor Cs is sufficiently small. As a result, most of the video signal Vsig is basically stored in the pixel capacitance Cs. To be precise, the video signal Vsig (that is, the difference between Vsig-Vss1) with respect to the reference potential Vss1 is stored in the pixel capacitor Cs. Therefore, the input voltage Vgs applied between the gate G and the source S of the driving transistor Trd is equal to the sum of the threshold voltage Vth detected and saved earlier and the difference (Vsig-Vss1) sampled at this time. That is, the input voltage Vgs is equal to (Vsig-Vss1+Vth). In order to make the following explanation simple, we assume that the reference potential Vss1 is 0V. At this time, the input voltage Vgs is equal to (Vsig+Vth), as shown in the timing chart shown in FIG. 3. The process of sampling the video signal Vsig continues to timing T7, at which time the first control signal WS returns to the low level. That is, the period from timing T5 to timing T7 is the sampling period.

[0082] At timing T6 before timing T7 when the sampling period is about to end, the second control signal DS becomes a low level so that the switching transistor Tr4 is turned on. Thus, since the drive transistor Trd is connected to the power supply Vcc, the pixel circuit transitions from the non-light-emission period to the light-emission period. In this way, in the period from the timing T6 to the timing T7, the mobility compensation operation is realized in which the sampling transistor Tr1 has been kept in the on state and the switching transistor Tr4 has entered the on state. That is, according to the present embodiment, the mobility compensation operation is performed in the period from the timing T6 to the timing T7 in which the start stage of the light emission period overlaps with the later part of the sampling period before the light emission period. It should be noted that at the beginning of the sub-period during the light-emitting period, the sub-period serves as a sub-period for implementing the mobility compensation operation, and the light-emitting device EL is in a reverse bias state in which the light-emitting device EL does not emit light. In the mobility compensation period from timing T6 to timing T7, the output current Ids flows through the drive transistor Trd while the gate G of the transistor Trd is maintained at the potential of the video signal Vsig. The relationship of (Vsig-Vth)

[0083] At timing T7, the first control signal WS becomes a low level so that the sampling transistor Tr1 enters an off state. As a result, the gate G of the driving transistor Trd is disconnected from the data signal line SL, terminating the application of the video signal Vsig to the driving transistor Trd. Thereby, the potential appearing on the gate G of the driving transistor Trd can rise, and actually, the potential appearing on the gate G of the driving transistor Trd rises as the potential appearing on the source S of the driving transistor Trd rises. At the same time, the input voltage Vgs stored in the pixel capacitor Cs, which is the voltage between the gate G and the source S of the drive transistor Trd, is maintained at a level represented by the expression (Vsig-ΔV+Vth). As the potential appearing on the source S of the driving transistor Trd rises, the reverse bias state of the light emitting device EL is terminated, so that the output current Ids flows to the light emitting device EL, and the light emitting device EL starts to actually emit a light beam. The relationship between the output current Ids and the input voltage Vgs expressed by Equation 2 given below holds true at this time. Equation 2 is an equation obtained by replacing the expression (Vsig-ΔV+Vth) with the term of the input voltage Vgs in Equation 1 of the characteristics of the driving transistor Trd.

[0084] Ids=kμ(Vgs-Vth) 2 =kμ(Vsig-ΔV) 2...Equation 2

[0085] The symbol k in Equation 2 represents (1/2)(W/L)Cox. Equation 2 no longer contains the term of the threshold voltage Vth of the driving transistor Trd. That is, as apparent from Equation 2, the output current Ids supplied to the light emitting device EL no longer depends on the threshold voltage Vth of the driving transistor Trd. Basically, the drain current (or output current) Ids is determined by the voltage of the video signal Vsig. In other words, the light emitting device EL emits a light beam in accordance with the brightness of the video signal Vsig. However, at this time, the video signal Vsig is corrected by the feedback amount ΔV. This correction amount ΔV is also used to invalidate the influence of the coefficient mobility μ included in Equation 2. As a result, the drain current Ids mainly depends only on the video signal Vsig.

[0086] Finally, at timing T8, the second control signal DS rises to a high level so that the switching transistor Tr4 enters the off state. At this point, both the light emission and the field are over. Subsequently, the pixel circuit 2 proceeds to the next field, and repeats the threshold voltage compensation operation, the mobility compensation operation, and the light-emitting operation, the process of which is as described above.

[0087] However, the pixel circuit 2 in the exemplary reference embodiment of the image display device requires five transistors Tr1, Tr2, Tr3, Tr4, and Trd, three power supply lines Vss1, Vss2, and Vcc, and four gate lines (or scan lines). ) WS, DS, AZ1 and AZ2. The number of intersections of gate lines (or scan lines) and data signal lines, and gate lines (or scan lines) and power lines must also be relatively large. The large number of intersections reduces the output. In addition, it is difficult to achieve high fineness of wiring. In the case of fine panels, in order to increase yield, it is necessary to reduce the number of devices.

[0088]Fig. 4 is a block diagram showing the entire structure of the image display device provided by the present invention. The image display device is an active matrix type image display device with a threshold (Vth) compensation function. As shown in the figure, the active matrix type image display device includes a pixel array unit 1 and its peripheral circuits as main components. The peripheral circuit includes a horizontal selector 3, a write scanner 4, and a drive scanner 5. The pixel array unit 1 has pixel circuits 2 arranged to form a matrix. Each pixel circuit 2 is disposed at the intersection of the first scan line WS (or second scan line DS) positioned in the row direction of the matrix and the data signal line SL positioned in the column direction of the matrix. The pixel circuit 2 is R, G, and B pixels. The R, G, and B pixels are the three primary colors of R, G, and B that allow color display. However, it is not meant to limit the protection scope of the present invention to these features. The R, G, and B pixels each have their own pixel circuit 2. The data signal line SL is driven by the horizontal selector 3. The horizontal selector 3, as a signal unit, is usually implemented as a driver IC. The data signal line SL transmits a video signal. The first scan line WS is driven by the write scanner 4. It should be noted that a second scan line DS parallel to the first scan line WS is also provided. The second scan line DS is driven by the drive scanner 5. The write scanner 4 and the drive scanner 5 form a scanner unit. In each horizontal scanning period, the scanner unit sequentially drives the pixels in each row. When the pixel circuit 2 is selected by the first scan line WS, the pixel circuit 2 samples the video signal transmitted by the data signal line SL. When the pixel circuit 2 is selected by the second scan line DS, the pixel circuit 2 drives the light emitting device in the pixel circuit 2 according to the sampled video signal. In addition, the pixel circuit 2 is also controlled by the first scan line WS and the second scan line DS to implement a predetermined compensation operation.

[0089] The pixel array unit 1 described above is built on an insulating substrate such as a piece of ordinary glass to form a flat panel. Each pixel circuit 2 is made of amorphous silicon TFT or low temperature polysilicon TFT. In the case of the pixel array unit 1 composed of the pixel circuit 2 made of amorphous silicon TFT, the scanner unit is typically configured to be separated from the flat panel and connected to the TAB of the flat panel with a flexible cable. In the same way, the signal unit is configured as a driver IC located outside the flat panel and connected to the flat panel with a flexible cable. On the other hand, in the case of the pixel array 1 composed of the pixel circuit 2 made of low-temperature polysilicon TFT, the scanner unit, the signal unit, and the pixel array unit 1 are integrated into a single body on a flat panel. This is because both the signal and scanner units can also be formed of low-temperature polysilicon TFTs.

[0090] FIG. 5 is a block diagram showing the structure of the pixel circuit 2 incorporated in the image display device provided by the present invention as shown in FIG. 4. As shown in FIG. 5, the pixel circuit 2 includes a sampling transistor Tr1, a pixel capacitor Cs connected to the sampling transistor Tr1, a driving transistor Trd connected to the sampling transistor Tr1 and the pixel capacitor Cs, and a driving transistor Trd connected to the driving transistor Trd and the pixel capacitor Cs. The light emitting device EL and the switching transistor Tr4 for connecting the driving transistor Trd and the power source Vcc.

[0091] The first scan signal line WS provides a first scan signal to bring the sampling transistor Tr1 into a conductive state. When the sampling transistor Tr1 enters the conductive state, the sampling transistor Tr1 samples the potential of the video signal Vsig transmitted by the data signal line SL and stores the sampled potential in the pixel capacitor Cs. The pixel capacitor Cs supplies the input voltage Vgs to the gate G of the driving transistor Trd in accordance with the sampled video signal Vsig. In turn, the driving transistor Trd supplies the output current Ids corresponding to the input voltage Vgs to the light emitting device EL. It should be understood that the characteristics of the output current Ids depend on the threshold voltage Vth of the drive transistor Trd. The output current Ids generated by the driving transistor Trd causes the light emitting device EL to emit a light beam of brightness in accordance with the voltage of the video signal Vsig. The second scan signal line DS provides the second scan signal DS to bring the switching transistor Tr4 into a conductive state. When the switching transistor Tr4 enters the conductive state, the driving transistor Trd is connected to the power source Vcc during the light emitting period, which is a period in which the light emitting device emits light beams. On the other hand, in the no-light emission period, the switching transistor Tr4 enters an off state to disconnect the driving transistor Trd from the power supply Vcc.

[0092] The image display device is characterized in that, during the horizontal scanning period (1H), the scanner unit including the write scanner 4 and the drive scanner 5 outputs the first The control signal is applied to the first scan line WS connected to the write scanner 4 to make the sampling transistor Tr1 in a conductive state, and the second control signal is output to the second scan line DS connected to the drive scanner 5 to switch the transistor Tr4 is in the on state. In addition, the pixel circuit 2 compensates for the influence on the characteristics exhibited by the output current Ids of the drive transistor Trd. The exhibited characteristics are dependent on the threshold voltage Vth of the drive transistor Trd. The pixel circuit 2 executes: Cs reset preparation operation; compensation operation for storing voltage in the reset pixel capacitor Cs as a voltage for eliminating the influence of the threshold voltage Vth; sampling operation for sampling the potential of the video signal Vsig provided by the data signal line SL And the sampled potential is stored in the compensated pixel capacitor Cs.

[0093] On the other hand, during the horizontal scanning period (1H), the signal unit including the horizontal selector 3 (or the driver IC 3) switches between the first fixed potential VssH, the second fixed potential VssL, and the signal potential Vsig to pass The data signal line SL provides each pixel with a potential required for the preparatory operation, the compensation operation, and the sampling operation.

[0094] Specifically, first, after continuing to provide the video signal of the first fixed potential VssH of the high level, the horizontal selector 3 switches the video signal to the second fixed potential VssL of the low level to perform the preparation operation. Then, while maintaining the low-level second fixed potential VssL, a compensation operation is performed. Successively, the horizontal selector 3 switches the video signal from the second fixed potential VssL to the signal potential Vsig, allowing the sampling operation to be performed. The level selector 3 configured as a driver IC includes a signal generating circuit for generating a signal potential Vsig and a signal generating circuit for inserting the first fixed potential VssH and the second fixed potential VssL into the signal potential Vsig generated by the signal generating circuit in the synthesis process. The output circuit to generate a video signal convertible between the first fixed potential VssH, the second fixed potential VssL, and the signal voltage Vsig, and output the video signal to each data signal line SL. Preferably, the driver IC as the level selector 3 outputs a video signal in which a signal potential Vsig that does not exceed a normal rating and a first fixed potential Vssh that exceeds the rating is synthesized. In this case, the signal generating circuit in the driver IC only needs to have an ordinary withstand voltage to generate a signal potential Vsig that does not exceed the rated value, and on the other hand, only the output circuit must be able to withstand the high first that exceeds the rated value. A fixed potential VssH.

[0095] The output current Ids generated by the driving transistor Trd exhibits a characteristic that is dependent on the mobility μ of carriers in the channel region of the driving transistor Trd and the threshold voltage Vth of the driving transistor Trd. In order to deal with the influence of this dependence, after outputting a control signal to the second scanning line DS during the horizontal scanning period (1H), the scanner unit including the writing scanner 4 and the driving scanner 5 also controls the switching transistor Tr4. Specifically, in order to invalidate the influence of the dependence of the output current Ids on the carrier mobility μ in the channel region of the drive transistor Trd, the sampled signal potential Vsig is used to extract the output current Ids from the drive transistor Trd and operate In the process of negative feedback, it is fed back to the pixel capacitor Cs to compensate the input voltage Vgs for the influence of this dependence.

[0096] FIG. 6 is a diagram showing a model of the pixel circuit 2 applied in the image display device shown in FIG. 5. In order to make the model easy to understand, the video signal Vsig. sampled by the sampling transistor Tr1, the input voltage Vgs applied to the driving transistor Trd, the output current Ids generated by the driving transistor Trd, and the capacitive element Coled of the light emitting device EL are additionally shown. In addition, the first scan line WS connected to the gate of the sampling transistor Tr1 and the second scan line DS connected to the gate of the switching transistor Tr4 are represented as boxes, respectively. During the horizontal scanning period (1H), the pixel circuit 2 performs threshold voltage compensation preparation operations, actual compensation operations, and signal potential sampling operations. Therefore, the pixel circuit 2 can be set to include only three transistors Tr1, Tr2, and Tr4, one pixel capacitor Cs, and one light emitting device EL. Compared with the pixel circuit 2 used in the typical reference embodiment shown in FIG. 1, this pixel circuit 2 is used as a pixel circuit 2 including a threshold voltage compensation preparation operation, and at least two switching transistors can be removed. Therefore, it is also possible to remove the power supply and gate lines of the two removed switching transistors, making it possible to increase the yield of the pixel circuit 2. In addition, since the wiring of the pixel circuit 2 can be simplified, the fineness of the panel can also be enhanced.

[0097] Fig. 7 is a timing chart of the pixel circuit 2 shown in Figs. 5 and 6. With reference to FIG. 7, the operations implemented by the circuits shown in FIGS. 5 and 6 can be explained in more detail and accurately as follows. FIG. 7 shows a waveform diagram of the control signals provided by the first and second scan lines WS and DS along the time axis. In order to simplify the figure, every detail of the control signal is indicated by the symbol indicating the scan line that transmits the special control signal. In addition, the waveform of the video signal applied to the data signal line SL is also shown along the time axis T. As shown in the figure, during each horizontal scanning period (1H), the video signal is sequentially switched between the high-level first fixed potential VssH, the low-level second fixed potential VssL, and the signal potential Vsig. The signal potential Vsig represents the true potential of the video signal. Since the sampling transistor Tr1 is an N-channel transistor, the first control signal transmitted by the first scan line WS is an active high signal set at a high level in an active state, and is set at a low level to disable the signal. On the other hand, because the switching transistor Tr4 is the P-channel transistor, the second control signal transmitted by the second scan line in the DS is an active low signal set at a low level in the active state and is set at High level. It should be understood that FIG. 7 not only shows the timing chart of the first and second control signal waveforms provided by the first and second scan lines WS and DS, respectively, but also shows the appearance of the gate G and the source S of the driving transistor Trd. Timing chart of potential waveform.

[0098] In the timing chart shown in FIG. 7, the period between timings T1 to T8 is one field (1f). During the 1f period, the pixel rows are sequentially scanned once. The timing chart shows the waveforms of the first and second control signals WS and DS applied to the pixels of each row.

[0099] Initially, at the field start timing T1, the second control signal DS rises from the low level to the high level, causing the switching transistor Tr4 to be in an off state, and thus, the driving transistor Trd is disconnected from the power supply Vcc. Thus, the light emission is terminated, and the non-light emission period starts. As a result, since the drive transistor Trd is not powered from the power source Vcc, the potential appearing on the gate G and source S of the drive transistor Trd is pulled down to the off voltage (or threshold voltage) VthEL of the light emitting device EL.

[0100] Subsequently, at timing T2, the first control signal WS rises from a low level to a high level, so that the sampling transistor enters a conductive state. In order to shorten the writing time for writing the video signal to the pixel capacitor Cs, it is desirable to increase the signal line voltage to the high-voltage first fixed potential VssH at the timing T2 before the sampling transistor Tr1 enters the conductive state. As the sampling transistor Tr1 enters the on state, a high-level first fixed potential VssH is applied to the gate G of the driving transistor Trd as a gate potential and written to the pixel capacitor Cs. At that time, the potential appearing on the source S of the driving transistor Trd is also raised by the coupling provided by the pixel capacitor Cs as a coupling between the gate G and the source S of the driving transistor Trd. However, the potential appearing on the source S of the drive transistor Trd only temporarily rises before the voltage is discharged to the ground potential through the light emitting device EL. Thus, finally, the potential appearing on the source S of the driving transistor Trd is at the off voltage (or threshold voltage) VthEL of the light emitting device EL. At that time, the gate voltage is maintained at the high-level first fixed potential VssH.

[0101] At timing Ta, by maintaining the sampling transistor Tr1 in the on state, the voltage appearing on the data signal line SL is pulled down to the low-level fixed potential VssL. Due to the coupling effect of the pixel capacitor Cs, the change in the signal line voltage extends to the potential appearing at the source of the drive transistor Trd. The amount of change due to coupling propagation is expressed by the following formula:

[0102] Cs/(Cs+Coled)×(VssH-VssL)

[0103] At that time, the potential appearing on the gate of the driving transistor Trd is VssL, and the potential appearing on the source of the driving transistor Trd is expressed by the following formula:

[0104] VthEL-Cs/(Cs+Coled)×(VssH-VssL)

[0105] Because the potential appearing on the source of the driving transistor Trd is lower than the cut-off voltage (or threshold voltage) VthEL of the light emitting device EL, that is, because a negative (or reverse) bias is applied to the light emitting device EL, the light emitting device EL enters Deadline. In this case, even after completion of the threshold voltage compensation operation and the mobility compensation operation performed thereafter, it is desirable to maintain the potential appearing on the source of the drive transistor Trd at a value that allows the light emitting device EL to continue to be in the off state. of. In addition, the input voltage Vgs (>Vth) is obtained by introducing coupling to perform preparation for the threshold voltage compensation operation. Thus, even in the pixel circuit 2 excluding some of the switching transistors and their gate lines and power supply lines, preparation for the threshold voltage compensation operation can be performed. That is, the period from the timing T2 to the timing Ta is the threshold voltage compensation preparation period.

[0106] At timing T3, by maintaining the gate G at the second fixed potential VssL at the low level, the switching transistor Tr4 enters the conductive state to perform the threshold voltage compensation operation in the same manner as the typical reference implementation described previously. The current flows to the driving transistor Trd. The current keeps flowing until the driving transistor Trd enters the off state. As the driving transistor enters the off state, the potential appearing on the source of the driving transistor becomes equal to the difference (VssL-Vth). At this time, it is necessary to establish the relationship (VssL-Vth)

[0107] Then, at timing T4, the switching transistor Tr4 enters the off state to end the threshold voltage compensation operation. Therefore, the period from the timing T3 to the timing T4 represents the threshold voltage compensation period.

[0108] At timing T5 after the threshold voltage compensation operation performed during the period from timing T3 to timing T4 as described above, the signal of the data signal line changes from the low-level second fixed potential VssL to the signal potential Vsig. Thus, the potential Vsig of the video signal is stored in the pixel capacitor Cs. Compared with the equivalent capacitance Coled of the light emitting device EL, the capacitance of the pixel capacitor Cs is sufficiently small. As a result, almost all of the signal potential Vsig is stored in the pixel capacitor Cs. Therefore, the input voltage Vgs between the gate G and the source S of the driving transistor Trd is equal to the sum of the threshold voltage Vth previously detected and stored and the signal potential Vsig sampled this time. That is, the input voltage Vsig is equal to (Vsig+Vth). The process of sampling the signal potential Vsig continues until the timing T7 when the first control signal WS returns to the low level. That is, the period from timing T5 to timing T7 is the sampling period.

[0109] The pixel circuit according to the present invention not only realizes the influence of the threshold voltage Vth of the driving transistor Trd to compensate the operation of the driving transistor Trd, but also realizes the influence of the influence of the carrier mobility μ in the channel region of the driving transistor Trd to compensate driving. Operation of transistor Trd. As will be described in detail later, the operation of compensating the driving transistor Trd for the influence on the mobility μ of carriers is performed in the period from the timing T6 to the timing T7. In short, the compensation amount ΔV must be subtracted from the input voltage Vgs.

[0110] At timing T7, the first control signal WS changes to a low level to cause the sampling transistor Tr1 to enter the off state. As a result, the gate G of the driving transistor Trd is disconnected from the data signal line SL, terminating the application of the video signal Vsig to the driving transistor Trd. Thereby, the potential appearing on the gate G of the driving transistor Trd can be increased, and in fact, the potential appearing on the gate G of the driving transistor Trd rises as the potential appearing on the source S of the driving transistor Trd rises. At the same time, the input voltage Vgs held in the pixel capacitor Cs, which is the voltage between the gate G and the source S of the drive transistor Trd, is maintained at a level represented by the expression (Vsig-ΔV+Vth). As the potential appearing on the source S of the driving transistor Trd rises, the reverse bias state of the light emitting device EL is terminated, so that the output current Ids flows into the light emitting device EL, and the light emitting device EL starts to actually emit a light beam. At that time, if the relationship between the current output current Ids and the input voltage Vgs is true, it is expressed by Equation 2 given previously. Equation 2 no longer includes the threshold voltage Vth term. That is, it is obvious from Equation 2 that the output current Ids applied to the light emitting device EL is no longer affected by the threshold voltage Vth of the driving transistor Trd. Basically, the drain current (output current) Ids is determined by the voltage of the video signal Vsig. In other words, the light emitting device EL emits light according to the brightness of the signal voltage Vsig of the video signal. At that time, the video signal is corrected by the feedback amount ΔV, which is also used to invalidate the influence of the mobility μ included in Equation 2. As a result, the drain current Ids mainly depends only on the video signal Vsig.

[0111] Finally, at timing T8, the second control signal DS rises to a high level so that the switching transistor Tr4 enters the off state. At this time, the light-emitting operation ends and the field ends. Subsequently, the pixel circuit 2 proceeds to the next field to repeat the compensation preparation operation, the threshold voltage compensation operation, the mobility compensation operation, and the light emission operation as described above.

[0112] As shown in FIG. 7, in the horizontal scanning period (1H), in order to eliminate the influence of the threshold voltage Vth, the pixel circuit 2 continuously performs preparation operations, compensation operations, and sampling operations. As shown in FIG. 5, the pixel circuit 2 only includes three Transistor and a capacitor. Therefore, the number of elements constituting the pixel circuit 2 can be significantly reduced compared with the typical reference implementation described previously. However, because the number of pixels increases with the increase in panel fineness, the horizontal scanning period allocated to each row of pixels is inevitably shortened. In addition, even if a high-frequency driving method that improves image quality is adopted, the horizontal scanning period in the high-frequency driving method is shortened. When the horizontal scanning period is shortened in this way, in some cases, it is difficult to complete the threshold voltage compensation preparation operation and the actual threshold voltage compensation operation in one horizontal scanning period. For this reason, a display device for a high-definition panel and a driving method of a high-frequency drive panel is required. A typical improved high-level implementation is explained as follows.

[0113] In a typical improved advanced implementation, the number of elements that make up the pixel circuit 2 with a threshold voltage compensation function is less than the number of elements in the previous typical improved implementation, and in addition, a high-definition A display device driving method for a high-frequency panel and a high-frequency drive panel. In a typical improved advanced implementation manner, the threshold voltage compensation preparation operation and the actual threshold voltage compensation operation performed in one horizontal scanning period so far are implemented at different times distributed among multiple horizontal scanning periods. And in this case, it can be ensured that the total work cycle is approximately the same as that shown in the timing diagram shown in FIG. 7. In the above-mentioned time distribution method, it is possible to shorten the sub-part including the horizontal scanning period as a sub-period occupied by, for example, the threshold voltage compensation preparation operation or the actual threshold compensation operation. Therefore, since the sub-period allocated to the threshold voltage compensation preparation operation or the actual threshold voltage compensation operation is shortened, it is possible to ensure that there is sufficient time for sampling the signal potential during the horizontal scanning period.

[0114] Figure 14 shows a timing diagram of operations implemented by a typical improved advanced implementation. To make the figure easy to understand, each part that is the same as the similar device shown in FIG. 7 is denoted by the same reference numeral or the same reference numeral as the similar element.

[0115] As shown in the figure, at timing T1, the switching transistor Tr4 enters an off state, causing the light emitting device EL to enter a non-light emitting period. At that time, since power is not supplied from the power source Vcc, the potential appearing on the source S of the driving transistor Trd is pulled down to the threshold voltage VthEL of the light emitting device EL.

[0116] Next, the sampling transistor Tr1 enters the conductive state during the period from the timing T21 to the timing Tb1. During this period, the video signal Sig is set at the first fixed potential VssH of a high level required to perform the threshold voltage compensation preparation operation. When the first sampling transistor Tr1 enters the ON state, the high-level first fixed potential VssH is applied to the gate G of the driving transistor Trd as the gate potential. At that time, the potential appearing on the source S of the driving transistor Trd also rises due to the influence of the coupling of the pixel capacitor Cs, the coupling being like the coupling between the gate G and the source S of the driving transistor Trd. However, the potential appearing on the source S of the driving transistor Trd only temporarily rises before the potential is discharged to the ground potential through the light emitting device EL. Thus, finally, the potential appearing on the source S of the driving transistor Trd is close to the off voltage (or threshold voltage) VthEL of the light emitting device EL. The first control signal WS for turning on the sampling transistor Tr1 is a pulse sequence having a certain pulse width, which is equal to a very short period from the timing T21 to Tb1. Therefore, the potential appearing on the gate G of the drive transistor Trd cannot reach the high-voltage first fixed potential VssH during the period from the timing T21 to Tb1. For this reason, the sampling transistor Tr1 enters the conductive state during the next period from the timing T22 to the timing Tb2. During this period, the video signal Sig is again at the high first fixed potential VssH. If necessary, the above-mentioned operation is repeated until the voltage appearing on the gate G of the driving transistor Trd reaches the first fixed potential VssH of the high level. In the case of the illustrated example, during the subsequent period from the timing T23 to the timing Tb3 and the subsequent period from the timing T24 to the timing Tb4, this operation is performed twice more. So the same operation was implemented four times.

[0117] Then, after the fourth operation, when the video signal Sig is pulled down to the low-level second fixed potential VssL, the sampling transistor Tr1 enters the conductive state so that the potential appearing on the gate G of the driving transistor Trd changes from the high-level first A fixed potential VssH is changed to a low level second fixed potential VssL. Regarding the change of the potential appearing on the gate G of the driving transistor Trd, the relational expression Vgs>Vth is established, allowing the preparation for the threshold voltage compensation operation to be completed. When the sampling transistor Tr1 enters the conductive state, the switching transistor Tr4 also enters the conductive state during the period from the timing T31 to the timing T41, allowing current to flow to the driving transistor Trd to implement the threshold voltage compensation operation. In the same way, the threshold voltage compensation operation can also be distributed among multiple cycles. Because the pulse width of the second control signal DS (ie, the period from timing T31 to timing T41) is short, the sampling transistor Tr1 and the switching transistor Tr4 need to be repeatedly turned on to complete the threshold voltage compensation operation. In the example shown in the figure, the sampling transistor Tr1 and the switching transistor Tr4 enter the ON state multiple times during the period from the timing T31 to the timing T41.

[0118] Finally, during the period from the timing T5 to the timing T7, the sampling transistor Tr1 is turned on, so that the signal voltage Vsig is stored in the pixel capacitor Cs. During the period from the timing T5 to the timing T6 to the timing T7 in the period of the timing T7, the mobility compensation operation is performed before the light emission period is started.

[0119]As described above, the pixel circuit with reduced transistors, power supply lines, and gate lines can implement threshold voltage compensation preparation operations and threshold voltage compensation operations even for panels that perform high-frequency operations and panels with high fineness. It should be understood that in the typical improved advanced reference implementation, when the sampling transistor Tr1 enters the on state, the switching transistor Tr4 also enters the on state to perform the mobility compensation operation. However, in the case where the operations of the sampling transistor Tr1 and the switching transistor Tr4 do not overlap with each other and therefore the mobility compensation operation is not implemented, even in simple threshold voltage compensation, wiring can be provided in the same manner and the transistor cost can also be reduced. Quantity.

[0120] As described above, in the horizontal scanning period, the scanner unit outputs a control signal to the gate of the transistor in order to control the pixel circuit 2. Under the control of the scanner unit, the pixel circuit 2 implements a compensation operation on the pixel capacitor Cs as an operation to eliminate the influence of the dependence of the output current generated by the drive transistor Trd on the threshold voltage Vth of the drive transistor Trd, and implement the sampling video signal Sig And the operation of storing the sampled video voltage Vsig in the pixel capacitor Cs that has been subjected to the compensation operation. In addition, the scanner unit also utilizes the horizontal scanning period allocated to the previous row of the current row. The current row includes the pixel capacitance of the pixel circuit under observation, so as to distribute the compensation operations performed on the pixel capacitor Cs of the pixel circuit under observation. Between time slots, each time slot is included in one of the horizontal scanning periods utilized. . Specifically, the scanner unit has a write scanner 4 and a drive scanner 5 that respectively generate the first control signal WS and the second control signal DS in the horizontal scanning period, so as to control the conduction of the sampling transistor Tr1 and the switching transistor Tr4. Disconnect implementation control. The pixel circuit 2 implements a compensation process on the pixel capacitor Cs as an operation to eliminate the influence of the dependence of the output current Ids generated by the drive transistor Trd on the threshold voltage Vth of the drive transistor Trd. The compensation process includes a compensation preparation operation to reset the pixel capacitor Cs and an actual compensation operation to eliminate the influence of the threshold voltage Vth after the voltage stored in the pixel capacitor Cs has been reset. After the compensation operation, a sampling operation is performed to sample the video signal Sig and store the sampled signal potential Vsig in the compensated pixel capacitor Cs. As mentioned above, the scanner unit also utilizes the horizontal scanning period all assigned to the previous row of the current row, the current row includes the pixel capacitance of the pixel circuit under observation, so as to distribute the compensation operation performed on the pixel capacitor Cs of the pixel circuit under observation. Among the multiple time slots, each time slot is included in one of the utilized horizontal scanning periods. .

[0121] In order to enhance the fineness of the panel, it is necessary to reduce the number of devices. As described above, the threshold voltage compensation operation is implemented by using negative coupling, and, in addition, its preparation period is divided into a plurality of sub-periods, and the operation is performed in each sub-period. However, in the case of a large-capacitance light-emitting device, the discharge time of the coupling voltage as the potential appearing on the source S of the drive transistor Trd inevitably becomes longer. Therefore, in order to have a desired voltage between the source S and the gate G of the driving transistor Trd, many negative coupling operations are inevitably required. For this reason, there are problems caused by the complexity of the panel.

[0122] In order to solve the above-mentioned problems, the present invention provides another typical high-level improved reference implementation. Fig. 15 shows a timing chart of another preferred embodiment of the present invention. In order to make the figure easy to understand, each component that is the same as the similar element shown in FIG. 14 is denoted by the same reference symbol or the same reference numeral denote the similar element. In this embodiment, capacitive coupling is used to implement threshold voltage compensation operations. The coupling operation is performed multiple times by being distributed in multiple time slots. The pulse width corresponding to the time slot is long enough for the light emitting device to discharge its potential. Therefore, the number of negative couplings per row (each row) can be reduced. Specifically, during the period from the timing T21 to the timing Tb1, the data signal line SL is set to the high-level first fixed potential VssH required for preparation for the threshold voltage compensation operation, and the sampling transistor Tr1 enters the conductive state. Therefore, during the period from the timing T21 to the timing Tb1, the first fixed potential VssH of a high level is applied to the gate G of the driving transistor Trd. At that time, due to the influence of the coupling provided by the pixel capacitor Cs, the potential appearing on the source S of the driving transistor Trd rises. However, the potential appearing on the source S of the drive transistor Trd only temporarily rises before the voltage is discharged to the ground potential through the light emitting device EL. Therefore, the potential appearing on the source S of the driving transistor Trd is finally at the off voltage (or threshold voltage) Vth of the light emitting device EL. Next, after a waiting time such as 5H is turned off from the light emitting device EL, during the period from the timing T22 to the timing Tb2, the data signal line SL is set at the first fixed potential VssH of the high level, and the sampling transistor Tr1 is brought into conduction State to implement the second compensation preparation operation. By performing the second compensation preparation operation, the potential appearing on the gate G of the driving transistor Trd reaches the first fixed potential VssH of the high level, and it is no longer necessary to increase the voltage change. That is, the required voltage between the gate G and the source S of the driving transistor Trd can be obtained.

[0123] In the driving operation shown in the timing chart of FIG. 14, the driving operation is a driving operation as a typical advanced improved reference implementation of a pixel circuit including light-emitting devices each having a large capacitance. Before the light-emitting device EL is turned off, It takes a long time to reduce the coupling voltage. When the potential appearing on the gate G of the driving transistor Trd rises to the first fixed potential VssH of the high level, a coupling voltage is introduced. For this reason, after the sampling transistor Tr1 enters the off state, the potential appearing on the gate G also decreases as the potential appearing on the source S of the driving transistor Trd decreases. Therefore, after that, even if the sampling transistor Tr1 enters the off state multiple times, the potential appearing on the gate G inevitably keeps falling until the source S is turned off by the light emitting device EL. As a result, in order for the potential appearing on the gate G to reach the voltage required between the gate G and the source S of the driving transistor Trd, many driving control pulses of the first scanning line WS are required.

[0124] In order to solve the above-mentioned problem, in another embodiment of the present invention, in order to implement the threshold voltage compensation preparation operation as shown in FIG. 15, the two consecutive lines applied from the first scan line WS to the gate G of the sampling transistor Tr1 The time between the driving control pulses is set to such a value that the light emitting device is completely turned off at the end of the interval. Then, after repeated implementation of the threshold voltage compensation preparation operation for many times, the potential appearing on the gate G reaches the first fixed potential VssH of the high level, and there is no need to increase the voltage change. In other words, by repeatedly implementing the threshold voltage compensation preparation operation multiple times, the voltage required between the gate G and the source S of the driving transistor Trd can be obtained. Therefore, a sufficient interval between two consecutive pulses that trigger the threshold voltage compensation preparation operation reduces the number of pulses compared to the number of pulses in a typical advanced improved reference implementation.

[0125] As described above, in the case of another embodiment of the present invention, in the horizontal scanning period (1H), it is implemented by changing the potential appearing on the gate G of the driving transistor Trd from a high level to a low level. The threshold voltage compensation preparation and the threshold voltage compensation operation, and, in the same horizontal scanning period (1H), the operations of sampling the video signal and storing the sampled video signal in the pixel capacitor Cs are performed. By implementing these operations, the three power lines required by the conventional image display device can be integrated in a single unit with only one shared line, which also performs all the functions of the power line of the integrated power supply. In addition, the number of power supply line lines, the number of gate lines, and the number of switching transistors can be reduced, so that the pixel circuit is configured to include only three transistors and one pixel capacitor. Therefore, the output of the panel can be increased. In addition, because the layout can be simplified, the fineness of the image display device can be enhanced. In the case of this embodiment, as the sampling transistor Tr1 enters the conductive state, the switching transistor Tr4 also enters the conductive state in order to implement the mobility compensation operation. However, it should be noted that even in a simple threshold voltage compensation operation in the case where the operation groups of the sampling transistor Tr1 and the switching transistor Tr4 are not overlapped with each other and therefore the row mobility compensation operation is not implemented, the wiring can be provided in the same manner, And the number of transistors can also be reduced.

[0126] FIG. 8 is a diagram showing the state of the pixel circuit 2 performing the mobility compensation operation during the period from the timing T6 to the timing T7. As shown in the figure, in the mobility compensation period from timing T6 to timing T7, both the sampling transistor Tr1 and the switching transistor Tr4 are in the on state, but the driving transistor Trd is in the off state. In these states, the potential appearing on the source S of the drive transistor Trd is equal to the difference (VssL-Vth). The potential appearing on the source S of the driving transistor Trd is also the potential appearing on the anode of the light emitting device EL. As described earlier, by setting the difference (VssL-Vth) to a value smaller than the threshold VthEL of the light emitting device EL, that is, (VssL-Vth)

[0127] FIG. 9 is a graph showing a graph, each curve representing Equation 2 representing the characteristics of the driving transistor Trd as described previously. The vertical axis represents the output current Ids, and the horizontal axis represents the video signal Vsig. Equation 2 is also written at the bottom of the graph. For comparison, the curves shown in FIG. 9 represent the characteristics of pixels 1 and 2, respectively. The pixel 1 includes a driving transistor Trd having a relatively large mobility μ. On the other hand, the pixel 2 includes a driving transistor Trd having a relatively small mobility μ. In the case of a driving transistor Trd implemented as a thin film transistor or the like, the mobility μ of the transistors are inevitably different from each other. For example, even if the video signal Vsig of the same level is applied to the gates of the pixels 1 and 2, the output current Ids1` flowing through the pixel circuit 1 including the drive transistor Trd having a relatively large mobility μ is different from the output current Ids1` flowing through the pixel circuit 1 including the driving transistor Trd having a relatively large mobility μ. The output current Ids2' of the pixel circuit 2 of the driving transistor Trd with a small mobility μ is greatly different in magnitude, unless some compensation is implemented on the driving transistor Trd to eliminate the influence of the difference in mobility μ. Because the difference in the output current Ids between the transistor and the transistor is actually caused by the unavoidable difference in mobility μ between the transistor and the transistor as described above, the uniformity of the display screen is lost.

[0128]In the present invention, the output current Ids is fed back to the input voltage side in a negative feedback operation mode, so as to eliminate the influence of different mobility. It is obvious from the formula expressing the characteristics of the driving transistor Trd that the greater the mobility, the greater the output current Ids. Therefore, the greater the mobility, the greater the amount of negative feedback ΔV. As shown by the graph in FIG. 9, the negative feedback amount ΔV1 of the pixel 1 including the driving transistor Trd having a relatively large mobility μ is larger than the negative feedback amount ΔV2 of the pixel 2 including the driving transistor Trd having a relatively small mobility μ. Therefore, since the greater the mobility, the greater the amount of negative feedback ΔV, so the influence of different mobility can be suppressed. As shown in the figure, the compensation operation of applying the negative feedback amount ΔV1 to the pixel 1 including the drive transistor Trd having a relatively large mobility μ results in its output circuit Ids1 being much smaller than the output current Ids1'. On the other hand, the compensation operation of applying the negative feedback amount ΔV2 to the pixel 2 including the drive transistor Trd having a relatively small mobility μ results in its output circuit Ids2 being not much smaller than the output current Ids2'. This is because the amount of negative feedback ΔV2 is smaller than the amount of negative feedback ΔV1. As a result, the output current Ids1 generated by the pixel 1 including the driving transistor Trd having a relatively large mobility μ is almost equal to the output current Ids2 generated by the pixel 2 including the driving transistor Trd having a relatively small mobility μ, meaning that the migration is eliminated The impact of the rate. In the entire video signal Vsig range from black level to white level, the influence of mobility is completely eliminated. Therefore, the uniformity of the display screen is quite high. In general, in the case of pixel circuits 1 and 2 having different mobilities, the negative feedback amount ΔV1 is set to a value larger than the negative feedback amount ΔV2. In other words, the greater the mobility, the greater the decrease in output current Ids. As a result, the different pixel currents caused by the different mobility are converted to almost uniform currents, eliminating the influence caused by the different mobility.

[0129] Next, referring to FIG. 10, a digital analysis of the above-mentioned mobility compensation is performed. In the following digital analysis, as shown in FIG. 10, the symbol V represents a variable representing the potential appearing on the source S of the driving transistor Trd. At this time, both the sampling transistor Tr1 and the switching transistor Tr4 have entered the conducting state. The drain current Ids flowing through the driving transistor Trd is expressed by Equation 3 as follows:

[0130] Ids=kμ(Vgs-Vth) 2 =kμ(Vsig-V-Vth) 2...Equation 3

[0131] Among them, the symbol V represents the potential appearing on the source S of the driving transistor Trd.

[0132] As shown in FIG. 4, the equation Ids=dQ/dt=CdV/dt representing the relationship between the drain current Ids and the capacitance C (=Cs+Cold) holds true, where the symbol Cs represents the capacitance of the pixel capacitor Cs, and Cold represents the capacitance of the light-emitting device Cold.

[0133] ∫ 1 C dt = ∫ 1 Ids dV

[0134] ⇔ ∫ 0 1 1 C dt = ∫ - Vth V 1 kμ ( Vsig - Vth - V ) 2 dV

[0135] ⇔ kμ C t = [ 1 Vsig - Vth - V ] - Vth V = 1 Vsig - Vth - V - 1 Vsig

[0136] ⇔ Vsig - Vth - V = 1 1 Vsig + kμ C t = Vsig 1 + Vsig kμ C t

[0137]...Equation 4

[0138] Substitute Equation 3 into Equation 4 and integrate both sides of the equation with respect to time. During the integration, the source voltage V in the initial state is -Vth, and the mobility compensation period from timing T6 to timing T7 is t. By solving this differential equation, the pixel current for the mobility compensation period t is given by Equation 5 as follows:

[0139] Ids = kμ ( Vsig 1 + Vsig kμ C t ) 2

[0140]...Equation 5

[0141] FIG. 11 is a graph showing that each curve represents Equation 5. The vertical axis represents the output current Ids, and the horizontal axis represents the video signal Vsig. The parameter values ​​t=0μs, t=2.5μs and t=5μs are used. The mobility μ is also used as a parameter. Regarding this parameter, a relatively large mobility of 1.2 and a relatively small mobility of 0.8 were used. The parameter t=0 μs indicates that there is no mobility compensation at all. Compared with t=0 μs, it can be clearly seen that the parameter t=2.5 μs indicates that the influence of the change in the drain current Ids due to the mobility change is sufficiently corrected. Specifically, the parameter t=0 μs represents a case in which there is a variation of the leakage power source of 40% because the mobility compensation operation is not performed. On the other hand, the parameter t=2.5 μs represents a case in which the influence of the change in leakage current Ids is suppressed by implementing mobility compensation of not more than 10%. However, t=5 μs, which represents a long mobility compensation period, on the contrary, indicates that the change in the drain current Ids caused by the mobility change inevitably increases. Therefore, in order to implement the mobility compensation operation, it is necessary to set the mobility compensation period t at an appropriate value. In the graph shown in FIG. 11, the appropriate value of the mobility compensation period t is approximately 2.5 μs.

[0142] As described above, in the present invention, during the horizontal scanning period (1H), the threshold voltage compensation preparation operation and the threshold voltage compensation preparation operation are performed by changing the potential appearing on the gate G of the driving transistor Trd from a high level to a low level during the horizontal scanning period (1H). Actual threshold compensation operation. Then, in the same horizontal scanning period, a sampling operation is performed to store the video signal in the pixel capacitor Cs. By performing these operations, the three power lines required in the conventional image display device can be integrated in a signal unit with only one shared signal line, which has all the power line functions of the original power line. In addition, the number of power supply lines, gate lines, and switching transistors can be reduced, so that the pixel circuit is configured to include only three transistors and one pixel capacitor. Therefore, the output of the panel can be increased. In addition, since the layout can be simplified, the fineness of the image display device can be enhanced. In the case of this embodiment, as the sampling transistor Tr1 enters the on state, the switching transistor Tr4 also enters the on state, so as to implement the mobility compensation operation. It should be understood, however, that in the case where the operations of the sampling transistor Tr1 and the switching transistor Tr4 do not overlap each other and therefore the mobility compensation operation is not implemented, even in simple threshold voltage compensation, wiring can be provided in the same manner and can also be reduced. The number of transistors. Further, in the pixel circuit according to the present embodiment, each of the sampling transistor Tr1 and the switching transistor Tr4 is an N-channel transistor. Only the drive transistor Trd is a P-channel transistor. However, any one of the sampling transistor Tr1, the driving transistor Trd, and the switching transistor Tr4 may be a P-channel transistor.

[0143] The following description explains an embodiment of executing a data driver composed of a horizontal selector as a signal unit applied in the image display device provided by the present invention. The data driver according to the present embodiment can convert the data signal line from a signal potential representing image data to a fixed potential to control the pixel circuit and vice versa. In addition, if the fixed potential of the control pixel circuit needs to have an amplitude greater than the maximum rated voltage of an ordinary data driver, only the switching function part can withstand high voltage. In this way, in the process of manufacturing the data driver, there is no need to change, such as changing the process to a process that can withstand high voltage, without changing the size of the circuit and increasing the spacing between the driver circuit IC pins, and the necessary functions of the data driver can be implemented. . The switch function part is provided close to the output terminal as a switch function part for switching the data signal line from a signal potential representing image data to a fixed potential to control the pixel circuit and vice versa.

[0144] FIG. 12A shows a pixel circuit applied in an image display device that can convert a data signal line from a signal potential representing image data to a fixed potential to control the pixel circuit and vice versa. FIG. 12B shows a timing chart of the waveform of the signal that drives the pixel circuit. The pixel circuit shown in FIG. 12A has three transistors Tr1, Tr4, and Trd, one pixel capacitor Cs, and one light emitting device EL. This circuit has a general form of a pixel circuit as shown in FIG. 5 as a pixel circuit according to an embodiment of the present invention. The video signal Vsig is supplied through the data signal line SL. According to the voltage of the video signal Vsig, the driving transistor Trd is turned on, and the light emitting device EL is driven to emit light of desired brightness. In this image display device, the characteristic change among the driving transistors Trd directly affects the quality of the display screen. In order to solve this problem, a compensation operation is performed by using a pixel capacitor in the compensation period to eliminate the influence of characteristic changes between the driving transistors Trd. In the compensation operation, the pulse waveform of the first control signal WS is applied to the gate of the sampling transistor Tr1 to apply the fixed potential Vst transferred by the data signal line SL as the control signal of the pixel circuit to the sampling transistor Tr1, and the second control signal DS The pulse waveform of is applied to the gate of the sampling transistor Tr4 to apply the power supply voltage to the driving transistor Trd via the switching transistor Tr4. In an ordinary image display device, the line for transmitting the fixed potential Vst connected to the drive/control system is separated from the line for transmitting the video signal Vsig connected to the image data system. That is, in an ordinary image display device, by applying a pulsed first control signal WS to the gate of the sampling transistor Tr1, the voltage Vst is applied to the gate of the driving transistor Trd via the sampling transistor Tr1 and a line connected to the driving/control system. However, the line is separated from the line for transmitting the video signal Vsig connected to the image data display system. By adopting such a configuration of a general image display device, the number of elements constituting the pixel circuit is increased, and thus the yield is reduced due to the defect of the pixel circuit. In addition, because each pixel circuit occupies a large area, the pixel circuit may have a bad influence on ordinary image display devices such as deterioration of physical resolution. In order to solve these problems, it is necessary to sufficiently reduce the number of elements constituting the pixel circuit, and to compensate the pixel circuit for the influence of the characteristic change among the driving transistors Trd. It is also necessary to separate the compensation period from the sampling period. The compensation period is used to provide the fixed potential Vst as the control signal of the pixel circuit to the gate of the driving transistor via the data signal line SL and the sampling transistor Tr1. The sampling period is used to The signal potential Vpc shown in FIG. 12B as a signal representing image data is supplied to the gate of the driving transistor via the data signal line SL and the sampling transistor Tr1.

[0145] At that time, it is not necessary to set the fixed potential Vst used as a pixel circuit control signal at the same level as the signal potential Vpc representing image data. Actually, there may be a case where the fixed potential Vst used as a pixel circuit control signal is higher than the signal potential Vpc representing image data, as shown in FIG. 12B. In addition, in some cases, the fixed potential Vst used as the pixel circuit control signal may be higher than the rated voltage of the data driver IC, which serves as a signal unit for outputting the fixed potential Vst and the signal potential Vpc. In addition, the signal output by the ordinary driver in the non-display period is an indeterminate voltage or a high-impedance output voltage. However, in the pixel circuit according to the present invention, the compensation period is separated from the sampling period, wherein the compensation period is used to provide the fixed potential Vst as the control signal of the pixel circuit to the gate of the driving transistor via the data signal line SL and the sampling transistor Tr1. The sampling period is used to provide the signal potential Vpc shown in FIG. 12B as a signal representing image data to the gate of the driving transistor via the data signal line SL and the sampling transistor Tr1. In some cases, the signal output by the signal unit The video signal Vsig needs to be fixed at the ground level GND.

[0146]FIG. 13 is a block diagram showing the structure of the data driver IC3, which satisfies the condition as the waveform of the control signal applied to the pixel circuit as described above. The large rectangular frame enclosed by solid lines is the output circuit 32 included in the data driver IC3. The output circuit 32 can withstand high voltage only by, for example, increasing the thickness of the circuit in the data driver IC 3 or the wiring film. By enabling the output circuit 32 to withstand high voltages, the signal generating circuit 31 included in the data driver IC3 can withstand high voltages as usual for manufacturing. The output circuit 32 includes switches SW1 and SW2 for switching voltage. However, since the control signal for driving the switches SW1 and SW2 is a logic signal for turning on and off the switches SW1 and SW2, the logic circuit for generating the logic signal need not be a circuit that can withstand high voltage.

[0147] The output terminals 31B of the signal generating circuit 31 respectively output voltages Vpc1 to Vpcn that do not exceed the maximum power supply voltage Vpc of the image data display system. The output voltage Vpci (i=1-n) is applied to the switch SW1 for selecting the output voltage Vpci or selecting a fixed voltage for controlling the pixel circuit. The fixed voltage used to control the pixel circuit is a logic pulse sequence having a height equal to the power supply voltage Vst of the driving/control system. The signal selected by the switch SW1 is applied to the switch SW2 to select the signal selected by the switch SW1 or the ground voltage GND. This is because during the operation of selecting the output voltage Vpci by the switch SW1 or selecting the fixed voltage Vst for controlling the pixel circuit, the output terminal 32B connected to the switch SW2 needs to output a voltage at the ground level GND. As a result, the output terminal 32B outputs an output voltage Vpci that does not exceed the maximum power supply voltage Vpc of the image data display system, a fixed voltage Vst having an amplitude equal to the power supply voltage of the driving/control system, or a voltage at the ground level GND.

[0148] Another embodiment of the present invention is explained in detail with reference to the drawings as follows. First, in order to clarify the background art of the present invention, the general structure of the active matrix type image display device is explained with FIG. 16. As shown in the figure, the image display device includes a pixel array unit 1, a horizontal selector 3, and a write scanner 4. The pixel array unit 1 is built on the panel to form a whole. The horizontal selector 3 and the write scanner 4 may be embedded inside the panel or attached to the outside of the panel. Each pixel circuit forming a pixel matrix in the pixel array unit 1 is arranged at the intersection of a scanning line WS oriented in the matrix row direction for supplying control signals and a data signal line SL oriented in the matrix column direction for supplying video signals. Point at. The scan line WS is connected to the write scanner 4 to sequentially output control signals to the scan line WS connected to the write scanner 4, thereby selecting the pixel circuit 2 in the row unit. On the other hand, the data signal line SL is connected to the horizontal selector 3 to supply the video signal to the selected pixel circuit 2.

[0149] FIG. 17 is a diagram showing a typical pixel circuit 2 applied to the image display device shown in FIG. 16. The structure of the pixel circuit 2 shown in the figure is the simplest, including two transistors T1 and T5, a pixel capacitor C1, and a light emitting device EL. The sampling transistor T1 is an N-channel TFT (thin film transistor), but the driving transistor T5 is this P-channel TFT. The pixel capacitor C1 is a film capacitor. The light-emitting device EL is a 2-terminal device (or diode) that uses a typical organic EL film as the light-emitting layer. The sampling transistor T1, the driving transistor T5, the pixel capacitor C1, and the light emitting device EL are built as a whole on the insulating substrate forming the panel.

[0150] The sampling transistor T1 is connected between the data signal line SL and the gate of the driving transistor T5. The gate of the sampling transistor T1 is connected to the write scanner 4 via the scan line WS. The gate of the driving transistor T5 is connected to the pixel capacitor C1. The source of the driving transistor T5 is connected to the power supply Vcc. The drain of the driving transistor T5 is connected to the anode of the light emitting device EL. The cathode of the light emitting device EL is connected to the ground.

[0151] In the horizontal scanning period, the control signal transmitted from the scanner 4 by the scanning line WS is applied to the sampling transistor T1 to make the sampling sampling transistor T1 in a conductive state. When the sampling transistor T1 enters the conductive state, the sampling transistor T1 samples the video signal transmitted from the horizontal selector 3 by the data signal line SL and stores the sampled video signal in the pixel capacitor C1. According to the video signal stored in the pixel capacitor C1, the driving transistor T5 supplies the drain current Ids to the light emitting device EL. Thus, the light emitting device EL emits light according to the brightness of the video signal.

[0152] According to the technology adopted by the pixel circuit 2 shown in FIG. 17, the input voltage Vgs applied to the gate of the driving transistor T5 varies with the video signal, and the output current Ids flowing through the driving transistor T5 to the light emitting device EL is controlled. In this embodiment, the source of the P-channel driving transistor T5 is connected to the power supply Vcc, and the transistor circuit is configured so that the driving transistor T5 always works in the saturation region. Thus, the driving transistor T5 functions as a constant current source, which operates according to Equation 1. That is, its drain is connected to the P-channel drive transistor T5 of the light emitting device EL, according to the input voltage applied between the gate and source of the drive transistor T5 regardless of the potential appearing on the drain of the drive transistor T5 Vgs can always supply a constant output current Ids to the light-emitting device.

[0153] FIG. 18 is a graph of I-V characteristics in which the light emitting device EL exhibits each I-V characteristic as a characteristic of the relationship between the voltage applied to the light emitting device EL and the current flowing through the light emitting device EL due to the application of the voltage. The light-emitting device EL, which is typically represented by an organic EL device, shows a trend of I-V characteristics with the passage of time. The curve drawn by the solid line represents the I-V characteristic of the initial state, and the curve drawn by the broken line represents the I-V characteristic exhibited by the light emitting device EL after the passage of time from the initial state. The voltage V indicated on the horizontal axis is the voltage appearing on the drain of the driving transistor T5 in FIG. 17. The current I indicated by the vertical axis is the output current supplied to the light emitting device EL by the driving transistor T5. As described above, the P-channel drive transistor T5 used in the pixel circuit 2 shown in FIG. 17 can always provide a constant output current Ids independent of the potential appearing on the drain of the drive transistor T5 to the light emitting device EL. Thus, even if the I-V characteristic of the light emitting device EL changes with the passage of time, the driving transistor T5 is not affected by the change with the I-V characteristic with the passage of time, and can always supply the constant current Ids to the light emitting device EL. Therefore, the light-emitting brightness of the light-emitting device EL does not change.

[0154] FIG. 19 is a diagram showing a typical structure of the pixel circuit 2. In order to make the figure easy to understand, each element corresponding to the element similar to the pixel circuit 2 in FIG. 17 is denoted by the same reference numeral, or the same reference symbol denotes the similar element. The pixel circuit 2 in FIG. 19 is different from the pixel circuit 2 in FIG. 17 in that: in the pixel circuit 2 in FIG. 19, the driving transistor T5 is an N-channel transistor instead of a P-channel transistor. In the case of the pixel circuit 2 shown in FIG. 19, the source of the driving transistor T5 is connected to the anode of the light emitting device EL. Therefore, the potential appearing on the source of the driving transistor T5 is affected by the change of the I-V characteristic that changes with the lapse of time, and also changes with the lapse of time. That is, the input voltage Vgs applied between the gate and source of the driving transistor T5 also inevitably changes with time. Thus, the amplitude of the output current applied to the light emitting device EL also changes with time, inevitably changing the light emission brightness of the light emitting device EL. In addition, the threshold Vth of the driving transistor T5 applied to the pixel circuit 2 also varies from transistor to transistor. Thus, it can be clearly seen from Equation 1 that since the output current Ids varies from transistor to transistor due to the difference in Vth between the transistor and the transistor and the Vgs varies with time, the brightness determined by the output current Ids It will inevitably vary from pixel to pixel.

[0155] The inventors of the present invention have developed an image display device capable of compensating for the light emission brightness of the light emitting device EL due to the degradation of the light emitting device EL over time and the change in the characteristics of the driving transistor. The reference implementation of a typical advanced development is shown in Figure 20. As shown in FIG. 20, the image display device has a pixel array unit 1, a horizontal selector 3, a write scanner 4, a drive scanner 5, a compensation scanner 7, and a second compensation scanner 8. The pixel array unit 1 includes a pixel circuit 2, which is arranged to form a pixel matrix. To make the illustration simple, only one pixel circuit 2 is shown. The pixel circuit 2 includes five transistors T1 to T5, one pixel capacitor C1, and one light emitting device EL in a structure having relatively many elements. In addition, this structure also has relatively many control lines for driving the pixel circuit 2. The nine control lines used to drive the pixel circuit 2 include four scan lines WS, DS, AZ and AZ2, one signal line SL, and four power lines respectively connected to four power sources Vcc, Vss, Vofs and Vcat. Thus, the nine control lines occupy most of the area allocated to the pixel circuit 2. In the scanning operation, the scanning lines WS, DS, AZ, and AZ2 are driven and controlled by the write scanner 4, the drive scanner 5, the compensation scanner, and the second compensation scanner 8, respectively. The data signal line SL transmits the input signal Vsig generated by the horizontal selector 3. In this typical implementation, each of the five transistors T1 to T5 is an N-channel transistor. The source S of the driving transistor T5 as the central device is connected to the anode of the light emitting device EL. The cathode of the light emitting device EL is connected to the power source Vcat. The drain of the driving transistor T5 is connected to the power supply Vcc via the switching transistor T4. The gate of the switching transistor T4 is connected to the second scan line DS. The gate G of the driving transistor T5 is connected to the data signal line SL via the sampling transistor T1. The gate of the sampling transistor T1 is connected to the first scan line WS. The gate G of the driving transistor T5 is also connected to the power supply Vofs via the switching transistor T3. The gate of the switching transistor T3 is connected to the scan line AZ2. The pixel capacitor C1 is connected between the gate G and the source S of the driving transistor T5. The source S of the driving transistor T5 is connected to the power supply Vss via the switching transistor T2. The gate of the switching transistor T2 is connected to the scan line AZ.

[0156] FIG. 21 shows a timing chart of operations performed with reference to the pixel circuit 2 shown in FIG. 20. The timing chart shows that the on/off states of the transistors T1 to T4 change with the time axis J. The states of the transistors T1 to T4 change according to the control signals transmitted by the first scan line WS, the scan line AZ, the scan line AZ2, and the second scan line AZ2, respectively. The first scan line WS, the scan line AZ, the scan line AZ2, and the second scan line AZ2 vary. The two scanning lines AZ2 are driven by the write scanner 4, the compensation scanner 7, the second compensation scanner 8 and the drive scanner 5, respectively. The timing chart also shows changes in the potential appearing on the gate G and the source S of the driving transistor T5. Before the timing J1, the switching transistor T4 is in an on state. Thus, the driving transistor T5 supplies the output current Ids to the light emitting device EL, so that the light emitting device EL enters a light emitting state.

[0157] At timing J1, the switching transistor T3 enters a conducting state, and the potential appearing on the gate G of the driving transistor T5 is pulled down to the voltage of the power supply Vofs. In addition, since the switching transistor T2 is also in the on state, the potential appearing on the source S of the driving transistor T5 is pulled down to the voltage of the power supply Vss. Since the voltage of the power supply Vss is lower than the threshold voltage Vthel of the light emitting device EL, no current flows to the light emitting device EL, so that the light emitting device EL is in a non-light emitting state. In addition, the voltage difference between the power sources Vofs and Vss is greater than the threshold voltage Vth of the driving transistor T5. By setting the voltage across the pixel capacitor C1 at such a level, the threshold voltage compensation operation is ready.

[0158] At timing J2, the switching transistor T2 enters an off state to disconnect the source S of the driving transistor T5 from the power source Vss, and therefore, the potential appearing on the source S rises. Current flows from the driving transistor T5 to the pixel capacitor C1, but when the potential difference Vgs across the pixel capacitor C1 reaches a value exactly equal to the threshold voltage Vth of the driving transistor T5, the current is turned off. As a result, such a voltage is accumulated in the pixel capacitor C1 so that the potential difference Vgs across the pixel capacitor C1 reaches a value exactly equal to the threshold voltage Vth of the driving transistor T5. This operation eliminates the influence of the threshold voltage Vth of the driving transistor T5.

[0159]At timing J3, the switching transistor T4 enters the off state, and then, at timing J4, the switching transistor T3 also enters the off state. At this point in time, all the transistors T1 to T4 are in the off state.

[0160] At timing J5, the sampling transistor T1 enters a conductive state to allow the video signal Vsig transferred by the data signal line SL to be applied to the gate G of the driving transistor T5. Next, at timing J6 at the end of the horizontal scanning period (1H) allocated to the pixel circuit 2, the sampling transistor T1 enters the off state. Thus, during the period from the timing J5 to the timing J6, the video signal Vsig transferred from the data signal line SL is stored in the pixel capacitor C1.

[0161] At timing J7, the switching transistor T4 enters a conductive state to connect the driving transistor T5 to the power supply Vcc, so that the output current Ids flows from the power supply Vcc into the driving transistor T5. The amplitude of the output current Ids is controlled to a fixed value by the input voltage Vgs stored in the pixel capacitor C1. Because the output current Ids flows, the potential appearing on the source S of the driving transistor T5 starts to rise. When the potential appearing on the source S of the driving transistor T5 exceeds the threshold voltage Vthel of the light emitting device EL, light emission is started. Through the bootstrap effect, the potential appearing on the source S of the driving transistor T5 also rises in an interlocked manner with the rising phenomenon of the potential appearing on the source S of the driving transistor T5. Therefore, the input voltage Vgs between the gate G and the source S of the driving transistor T5 is always maintained at a constant value by the pixel capacitor C1.

[0162] With reference to FIGS. 22 to 28, the following description explains a reference implementation of advanced development, which is described in detail and briefly by referring to FIGS. 20 and 21. First, in the light emitting state of the light emitting device EL, only the switching transistor T4 enters the on state as shown in FIG. 22. At that time, the driving transistor T5 has been set to operate in the saturation region. Thus, the magnitude of the output current Ids flowing through the light emitting device EL is determined by the input voltage Vgs applied between the gate G and the source S of the driving transistor T5 according to Equation 1 given earlier.

[0163] Next, in the non-light emitting state of the light emitting device EL, each of the switching transistor T3 and the switching transistor T2 is in the on state as shown in FIG. 23. At that time, the power supply Vss voltage is applied to the source S of the driving transistor T5, and the power supply Vofs voltage is applied to the gate G of the driving transistor T5. That is, the difference of (Vofs-Vss) is applied between the gate G and the source S of the driving transistor T5. When the difference of (Vofs-Vss) is applied between the gate G and the source S of the driving transistor T5, the output current Ids′ flows from the power supply Vcc to the power supply Vss, as shown in FIG. 23. In this case, in order to make the light emitting device in a non-light emitting state, it is necessary to set the power supply Vofs voltage and the power supply Vss voltage at such a value that the voltage Vel applied to the light emitting device EL is less than the threshold voltage Vthel and the power supply Vcat of the light emitting device EL. The sum of voltages. In addition, the switching transistor T2 can be turned on before the switching transistor T3 enters the conductive state, and vice versa.

[0164] Next, the switching transistor T2 enters the ON state as shown in FIG. 24. As shown in FIG. 25, the equivalent circuit of the light emitting device EL includes a diode Tel and a capacitor Cel. Therefore, as long as the relational expression Vel≤Vcat+Vthel holds, it means that the leakage current of the light emitting device EL is much smaller than the output current Ids flowing through the driving transistor T5, and the output current Ids flowing through the driving transistor T5 is in the pixel capacitors C1 and Cel accumulation. At that time, the voltage Vel appearing on the anode of the light emitting device EL increases with the passage of time, as shown in FIG. 26. The voltage Vel appearing on the anode of the light emitting device EL is exactly the voltage appearing on the source S of the driving transistor T5. After the predetermined period of time has elapsed, the input voltage Vgs applied between the gate G and the source S of the driving transistor T5 is equal to the threshold voltage Vth of the driving transistor T5. At that time, the following relationship holds:

[0165] Vel=Vofs-Vth≤Vcat+Vthel

[0166] After the threshold removal operation, each of the switching transistor T4 and the switching transistor T3 enters the off state. By making the switching transistor T4 into the off state earlier than the switching transistor T3, the influence of the voltage change appearing on the gate G of the driving transistor T5 can be suppressed. Then, the sampling transistor T1 enters a conducting state, so that the voltage appearing on the gate G of the driving transistor T5 is adjusted to the signal voltage Vsig, as shown in FIG. 27. At that time, the input voltage Vgs applied between the gate G and the source S of the driving transistor T5 according to Equation 6 is determined by the capacitance of the pixel capacitor C1, the parasitic capacitance Cel of the light emitting device EL, and the parasitic capacitance C2 of the driving transistor T5 . However, since the parasitic capacitance Cel of the light emitting device EL is larger than the capacitance of the pixel capacitor C1 and the parasitic capacitance C2 of the driving transistor T5, the input voltage Vgs applied between the gate G and the source S of the driving transistor T5 is approximately equal to (Vsig +Vth). But in this case, in order to simplify the formula, suppose Vof2=0.

[0167] Vgs = Cel Cel + C 1 + C 2 ( Vsig - Vofs ) + Vth ...Equation 6

[0168] When the operation of storing the signal potential Vsig in the pixel circuit 2 is completed, the switching transistor T4 enters a conductive state so that the voltage appearing on the drain D of the driving transistor T5 is increased to the voltage Vcc of the power supply. Since the voltage Vgs applied between the gate G and the source S of the driving transistor T5 is fixed, the driving transistor T5 outputs a constant current Ids" to the light emitting device EL. At that time, the voltage Vel of the light emitting device EL rises to the voltage Vx corresponding to the constant output current Ids shown in FIG. 28, and the light emitting device EL emits light.

[0169] Also in the above-mentioned pixel circuit, when the light-emitting period of the light-emitting device EL is long, the I-V characteristics inevitably change. As a result, the voltage appearing at point B shown in FIG. 28 also changes. However, since the voltage Vgs between the gate G and the source S of the driving transistor T5 is fixed, the driving transistor T5 outputs a constant current Ids to the light emitting device EL. Thus, even if the I-V characteristic changes, the constant output current Ids continues to flow all the time, and therefore, the light-emitting brightness of the light-emitting device EL does not change.

[0170] Next, let us consider the power lines and gate lines in the pixel circuit of the reference implementation of a typical advanced development. The pixel circuit includes 12 power supply lines, four power supplies Vcc, Vofs, Vss, and Vsig, and four gate lines WS, AZ, Az2, and DS for the three primary colors of R, G, and B. That is, the power supply line and the gate line occupy most of the area of ​​the pixel circuit. Therefore, it is difficult to enhance the fineness of the panel and increase the output of the pixel circuit.

[0171] To solve the above-mentioned problems, the present invention provides the circuit structure shown in FIG. 29. The pixel circuit structure includes only one pixel capacitor of three transistors. In addition, the pixel circuit structure for the three primary colors of R, G, and B has only three gate lines and three power supply lines.

[0172] As shown in the figure, the image display device according to this embodiment includes a pixel unit 1, a scanner unit, and a signal unit. The scanner unit has a write scanner 4, a drive scanner 5, and a power line scanner 9. The horizontal selector 3 serves as a signal unit. Each of the pixel circuits 2 that form a pixel matrix in the pixel array unit 1 is disposed at the intersection of the first scan line WS and the second scan line DS and the signal line SL, the first scan line WS and the second scan line DS The row direction orientation of the matrix is ​​used to provide control signals, and the signal line SL is oriented in the column direction of the matrix to provide video signals. The horizontal selector 3 serving as a signal unit supplies the video signal to the pixel circuit via the data signal line SL. The write scanner 4 in the scanner unit provides a first control signal via the first scan line WS. In the same way, the drive scanner 5 included in the scanner unit provides the second control signal via the second scan line DS. The first control signal WS and the second control signal DS are used to sequentially scan the pixel circuits 2 line by line. Each of the pixel circuits 2 includes a sampling transistor T1, a pixel capacitor C1 connected to the sampling transistor T1, a driving transistor T5 connected to the sampling transistor T1, an EL connected to the pixel capacitor C1 and the driving transistor T5, and The transistor T5 is connected to the switching transistor T4 of the power supply line VL. The first control signal transmitted by the first scan line WS causes the sampling transistor T1 to enter a conductive state, so that the sampling transistor T1 samples the signal potential Vsig of the video signal Sig transmitted by the signal line SL and stores the sampled signal potential Vsig in the pixel The capacitor C1. The voltage stored in the pixel capacitor C1 as the signal potential Vsig of the video signal Sig is applied between the gate G and the source S of the driving transistor T5 as the input voltage Vgs. Receiving the input voltage Vgs, the driving transistor T5 generates an output current Ids according to the input voltage Vgs and provides the output current Ids to the light emitting device EL. The output current Ids exhibits a characteristic dependent on the threshold voltage Vth of the driving transistor T5. The light emitting device EL is connected between the source S of the driving transistor T5 and the cathode potential Vcat. In the light-emitting period, the output current Ids provided by the driving transistor T5 to the light-emitting device EL drives the light-emitting device EL to emit light, and the light has a brightness according to the signal potential Vsig of the video signal Sig, which is applied to the driving transistor T5. Between the gate G and the source S. During the light-emitting period, the second scan line DS transmits a second control signal to make the switching transistor T4 into a conductive state, so as to connect the driving transistor T5 to the power line VL. On the other hand, during the non-light emitting period, the switching transistor T4 enters a non-conducting state, so that the driving transistor T5 is disconnected from the power supply line VL.

[0173] The feature of the present invention is that the write scanner 4 in the scanner unit outputs the first control signal WS to the sampling transistor T1 via the first scan line WS to turn the sampling transistor T1 on and off, and the drive in the scanner unit The scanner 5 also outputs a second control signal at DS to the switching transistor T4 via the second scan line to turn the switching transistor T4 on and off, so as to implement a compensation operation to compare the output current Ids with the threshold value of the driving transistor T5. The influence of the dependence of the voltage Vth is compensated for the pixel capacitor C1, and a sampling operation is performed to store the signal potential Vsig of the video signal Sig in the compensated pixel capacitor C1. In this case, the horizontal selector 3 as a signal unit converts the video signal Sig from the first fixed potential Vofs to the signal potential Vsig and vice versa in accordance with whether the pixel circuit 2 has performed a compensation operation or a sampling operation, so that the data signal The line SL outputs the first fixed potential Vofs required for the compensation operation during the compensation operation or the signal potential Vsig required for the sampling operation during the sampling operation to the sampling transistor T1 applied in the pixel circuit 2. Specifically, the horizontal selector 3 supplies the first fixed potential Vofs to the data signal line SL during the compensation operation, and then switches the data signal line SL to the signal potential Vsig during the sampling operation following the compensation operation.

[0174] The power supply line VL is arranged in the pixel array unit 1 in parallel to the first control signal line WS and the second control signal line DS. As mentioned before, the scanner unit includes a power supply line scanner 9 for scanning the pixel circuits 2 row by row from one row to another using the power supply line VL. In the same way, the writing scanner 4 uses the first scanning line WS and drives The scanner scans the pixel circuit 2 in the same manner as the second scan line DS. The power line scanner 9 supplies the potentials Vcc and Vss required during a predetermined operation period to the driving transistor T5 via the power line VL and the switching transistor T4. Specifically, during the compensation operation, the power supply line scanner 9 switches the power supply line VL from the standard potential Vcc to the potential Vss, and supplies the potential Vcc during the light emission period. In this way, in the compensation operation period, the potential Vss required for the operation is supplied to the driving transistor T5 via the power supply line VL and the switching transistor T4. Therefore, in the above embodiment, during the horizontal scanning period 1H allocated to one row of pixel circuits 2, the scanner unit outputs the first control signal WS to the first scanning line WS, and outputs the second control signal to the second scanning line DS. DS in order to implement compensation and sampling operations within 1H of the horizontal scanning period.

[0175]FIG. 30 shows a timing chart of operations performed by the image display device shown in FIG. 29. The timing chart shows a diagram representing that each of the sampling transistor T1 and the switching transistor T4 enters the on and off states at timing J along the time axis. In addition, the timing chart also shows a waveform diagram of the power supply voltage change on the power supply line VL and the signal voltage change on the data signal line SL. In addition, the timing chart also shows the change of the potential appearing on the gate G of the driving transistor T5 and the change of the potential appearing on the source S of the driving transistor T5.

[0176] As shown in the figure, before the timing J1 and after the timing T8, the pixel circuit 2 is in the light-emitting period. On the other hand, the period from the timing J1 to the timing J8 is a non-light emitting period. The period from the timing J4 to the timing J5 is a threshold compensation period in which the threshold voltage compensation operation is performed. In addition, the period from timing J6 to timing J7 is a sampling period, during which sampling operation is performed. On the other hand, the period from the timing J1 to the timing J4 is a compensation preparation period in which the compensation preparation operation is performed.

[0177] First, at timing J1, the switching transistor T4 enters an off state so that the driving transistor T5 is disconnected from the power supply voltage Vcc. Thus, the potential appearing on the gate G and the source S of the driving transistor T5 is pulled down. The potential appearing on the source S of the driving transistor T5 is exactly equal to the sum of (Vcat+Vthel), where the symbol Vcat represents the potential appearing on the cathode of the light emitting device EL, and the symbol Vthel represents the threshold voltage of the light emitting device EL. Next, at timing J2, the potential of the power supply line VL changes from the voltage Vcc to the voltage Vss. Subsequently, at timing J3, both the sampling transistor T1 and the switching transistor T4 enter a conducting state. At that time, the potential appearing on the power supply line VL is maintained at the voltage Vss, and the data signal line SL is set at a predetermined fixed potential Vofs. Since the sampling transistor T1 is in the on state, the fixed potential Vofs is applied to the gate G of the driving transistor T5. Since the switching transistor T4 is in the on state, the potential appearing on the source S of the driving transistor T5 is pulled down to the voltage Vss.

[0178] Next, at timing J4, the potential appearing on the power supply line VL changes from the voltage Vss back to the voltage Vcc. As a result, current flows from the driving transistor T5 to the pixel capacitor C1, and the potential appearing on the source S of the driving transistor T5 starts to rise. It should be noted that at this point in time, the light emitting device EL is in a reverse bias state. Thus, the light emitting device EL does not emit light. When the voltage applied between the gate G and the source S of the driving transistor T5 is equal to the threshold voltage Vth of the driving transistor T5, the driving transistor T5 enters the off state. Thus, a voltage whose amplitude is equal to the threshold voltage Vth is stored in the pixel capacitor C1.

[0179] Subsequently, at timing J5, the switching transistor T4 enters the off state. Next, at timing J6, the data signal line SL changes from the predetermined fixed potential Vofs to the signal potential Vsig. At that time, the sampling transistor T1 is maintained in an on state. Thus, the signal potential Vsig is stored in the pixel capacitor C1 and added to the threshold voltage Vth. Subsequently, at timing J7, the sampling transistor T1 enters the off state to complete the operation of storing the signal potential Vsig in the pixel capacitor C1. Next, at timing J8, the switching transistor T4 enters the conductive state to start the light-emitting period.

[0180] With reference to FIGS. 31 to 35, the following description will explain the operations performed by the pixel circuit 2 shown in FIGS. 29 and 30 as operations performed by the pixel circuit 2 provided by the present invention. First, only when the switching transistor T4 enters the on state, the light emitting state of the light emitting device EL exists, as shown in FIG. 31. Since the driving transistor T5 is designed to operate in a saturated state, at that time, according to Equation 1, the amplitude of the current flowing to the light emitting device EL is determined by the input voltage Vgs applied between the gate G and the source S of the driving transistor T5 to make sure.

[0181] Next, the switching transistor T4 enters the off state, as shown in FIG. 32. When the switching transistor T4 enters the off state, current no longer flows from the power supply to the light emitting device EL, so the light emitting device no longer emits light beams. At that time, the voltage appearing on the source S of the driving transistor T5 is equal to the sum of (Vcat+Vthel), where the symbol Vcat represents the potential appearing on the cathode of the light emitting device EL, and the symbol Vthel represents the threshold voltage of the light emitting device EL.

[0182] Next, when the power supply voltage is Vss and the signal potential is Vofs, both the sampling transistor T1 and the switching transistor T4 enter the conducting state, as shown in FIG. 33. When the signal voltage is Vofs and the sampling transistor T1 enters the conductive state, the gate G of the driving transistor T5 rises to the potential Vofs. In addition, since Vss is less than (Vcat+Vthel), the potential appearing at point A in the figure is the potential of the source S of the drive transistor T5, and the voltage appearing at point B in the figure is the drain of the drive transistor T5. The potential of the pole. In addition, since (Vofs-Vss) is greater than the threshold voltage of the driving transistor T5, the current flows to raise the potential appearing at point B to Vss, as shown in the figure. As described above, since the power supply voltage Vss is not higher than the sum of (Vcat+Vthel), the symbol Vcat represents the potential appearing on the cathode of the light-emitting device EL, and the symbol Vthel represents the threshold voltage of the light-emitting device EL, that is, due to the relationship Vss≤(Vcat+Vthel) holds, and the light-emitting device does not emit light.

[0183] In this state, the power supply voltage switches back to Vcc, as shown in Figure 34. By implementing this operation, the potential appearing at point B is again the potential of the source of the driving transistor T5, and the potential appearing at point A is again the potential of the drain of the driving transistor T5. The equivalent circuit of the light emitting device EL can be represented by a diode Tel and a capacitor Cel as shown in the figure. Therefore, as long as the relational expression Vel≤(Vcat+Vthel) holds, that is, until the leakage current of the light emitting device EL is less than the current flowing to the driving transistor T5, the current flowing into the driving transistor T5 is accumulated in the pixel capacitor C1 and the light emitting device EL. Cel. At that time, the voltage Vel rises with the passage of time. On the other hand, after a predetermined time has elapsed, the input voltage Vgs applied between the gate G and the source S of the driving transistor T5 is equal to the threshold voltage Vth. At that time, the relation Vel=Vofs-Vth≤Vcat+Vthel holds.

[0184] After a predetermined period of time, the switching transistor T4 enters the off state. Next, the signal voltage Vsig appearing on the data signal line SL is applied to the gate G of the driving transistor T5 as a desired signal voltage, as shown in FIG. 35. At that time, according to Equation 6 previously given, the input voltage Vgs applied between the gate G and the source S of the driving transistor T5 is determined by the capacitance of the pixel capacitor C1, the parasitic capacitance Cel of the light emitting device EL, and the driving transistor T5. The parasitic capacitance C2 is determined. However, since the parasitic capacitance Cel of the light emitting device EL is greater than the capacitance of the pixel capacitor C1 and the parasitic capacitance C2 of the driving transistor T5, the input voltage Vgs applied between the gate G and the source S of the driving transistor T5 is approximately equal to (Vsig+ Vth).

[0185] When the operation of storing the signal voltage Vsig in the pixel capacitor C1 is completed, the sampling transistor T1 enters the off state, and the switching transistor T4 enters the on state, so that the voltage appearing on the drain D of the driving transistor T5 rises to the power supply Vcc The voltage. Since the input voltage Vgs applied between the gate G and the source S of the driving transistor T5 is fixed, the driving transistor T5 outputs a constant current Ids" to the light emitting device EL. At that time, the voltage Vel of the light emitting device EL rises to the voltage Vx corresponding to the constant output current Ids" shown in FIG. 36, and the light emitting device EL emits a light beam.

[0186] Also in the above-mentioned pixel circuit, when the light-emitting time of the light-emitting device EL is long, the I-V characteristics inevitably change. As a result, the potential appearing at point B also changes. However, since the input voltage Vgs applied between the gate G and the source S of the driving transistor T5 is fixed, the driving transistor T5 always outputs a constant current Id to the light emitting device EL. Thus, even if the I-V characteristic changes, the constant output current Id keeps flowing, and therefore, the brightness of the emitted light of the light emitting device EL does not change. As mentioned above, the power supply voltage provided by the present invention also has two different amplitudes. Thus, with the existing gate driver, the image display device can be realized at low cost.

[0187] The modified version of the present invention is shown in Figure 37. The difference between the modified version of the present invention and the above-mentioned embodiment lies in that the operation timing of the switching transistor T4 of the modified version is different from the operation timing of this embodiment. In the case of the modified version of the present invention, the rise time of the switching transistor T4 can extend the limit of the threshold compensation period.

[0188] Since the present invention can suppress the influence of threshold changes between driving transistors, it is possible to obtain uniform image quality without unevenness and chromatic dispersion. In addition, since the power supply voltage provided by the present invention has two pulse waveforms of different sizes as described above, the existing gate driver can be used to realize the image display device at low cost. In addition, since the pixel circuit provided by the present invention has only a small number of components, including three transistors and one capacitor, it can be expected to obtain high fineness and high yield. Furthermore, for each of the RGB three originals, the pixel circuit provided by the present invention only includes three gate lines and three power lines. Therefore, the size of the area allocated to the pixel circuit can be reduced as the area of ​​the power supply line and the gate line line. As a result, high fineness and high yield can be expected. In addition, in the present invention, the voltages applied to the gate and source of the driving transistor are maintained at a constant level. Therefore, the output current flowing to the light emitting device EL does not change. As a result, even if the I-V characteristic of the light emitting device EL changes with the passage of time, the brightness of the light beam emitted by the light emitting device is no longer changed.

[0189] In addition, those of ordinary skill in the art should understand that various modifications, combinations, recombinations and changes that depend on design requirements and other factors are within the scope of the appended claims or their equivalents.