Bonding pad structure of a semiconductor device and method of fabricating the same

a technology of semiconductor devices and bonding pads, which is applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of bonding pads being downsized, bonding pads being subject to damage, and bonding pads being likely to suffer mechanical stress, etc., to achieve reliable bonding pads and large alignment margins
US20010054768A1Inactive Publication Date: 2001-12-27SAMSUNG ELECTRONICS CO LTD
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
SAMSUNG ELECTRONICS CO LTD
Publication Date
2001-12-27
Estimated Expiration
Not applicable · inactive patent

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Abstract

A bonding pad structure and a method of fabricating the bonding pad structure allow for a large assembly process margin in the process of connecting a lead tot he bonding pad structure. A first insulating layer is formed on a semiconductor substrate. A first conductive layer pattern is formed on a portion of the first insulating layer. The substrate and the first conductive layer pattern are covered with a second insulating layer. A second conductive layer pattern is formed on a portion of the second insulating layer so as to be disposed directly over the first conductive layer pattern. The resultant structure is covered with a third insulating layer. The third insulating layer and the second insulating layer are sequentially patterned to form a via hole through which the top surface of the second conductive layer pattern and a peripheral portion of the first conductive layer pattern are exposed. The patterning exposes the first conductive layer by extending an opening, preformed in a peripheral portion of the second conductive layer pattern, through the second insulating layer. Alternatively, the patterning can form an initial opening between the third insulating layer and the peripheral edge of the second conductive layer pattern, and then extend the opening through the second insulating layer. The via hole is then filled with a third conductive layer which is patterned and electrically connects the second and first conductive layer patterns. In this way, there is substantially no step between the top surface of the third conductive layer pattern where a beam lead is to be bonded and the third insulating layer having the via hole in which the third conductive layer pattern is formed.
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Description

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device and to a method of fabricating a semiconductor device. More particularly, the present invention relates to the bonding pad structure of a semiconductor device and to a method of fabricating the same.

[0003] This application is a counterpart of, and claims priority to, Korean patent application no. 2000-34902, filed Jun. 23, 2000, the contents of which are incorporated herein by reference in their entirety.

[0004] 2. Description of the Related Art

[0005] As is well known, semiconductor chips are sealed to protect them from external moisture and impact. In addition, a semiconductor device requires a plurality of bonding pads for delivering an electrical signal between its semiconductor chip and external electronics. During assembly, i.e., during a packaging process, the bonding pads of a semiconductor device are electrically connected to lead lines of a lead frame with conductive material such ...

Claims

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