Semiconductor device and method of manufacturing the same

Abstract

There is disclosed a semiconductor device having: a semiconductor substrate; a first gate electrode constructed of a multi-layered stack member provided in a memory region, formed with memory cells, of a surface area of the semiconductor substrate so that the first gate electrode is insulated by a first insulating layer from the semiconductor substrate; and a second gate electrode provided in a logic region, formed with a logic circuit for controlling at least the memory cells, of the surface area of the semiconductor substrate so that the second gate electrode is insulated by a second insulating layer from the semiconductor substrate, wherein said layer, brought into contact with the first insulating layer, of the first gate electrode and the layer, brought into contact with the second insulating layer, of the second gate electrode, are composed of materials different from each other. There is also disclosed a method of manufacturing a semiconductor device by defining a memory region for providing memory cells and a logic region for providing a logic circuit for controlling the memory cells, the memory and logic regions being isolated by a device isolation region on a semiconductor substrate; providing a first insulating layer on the semiconductor substrate; selectively removing said first insulating layer existing on the logic region in a surface area of the semiconductor substrate; stacking an amorphous silicon layer on the semiconductor substrate; and effecting a thermal treatment upon the semiconductor substrate in order to alter said amorphous silicon layer existing on said memory region into a polycrystalline semiconductor layer and to alter the amorphous silicon layer existing on the logic region into a silicon monocrystalline layer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-370313, filed on Dec. 4, 2001; the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION The present invention relates generally to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a DRAM embedded with a logic circuit and a DRAM and a manufacturing method thereof. It has been demanded to speed-up of operation of a system LSI. Responding to this demand, a plurality of types of devices having functions different from each other are mounted on a single semiconductor substrate. One example thereof is the system LSI including a logic circuit for controlling the DRAM, wherein the logic circuit and the DRAM are embedded into one single chip. Thus, the system LSI embedded with the logic circuit and the DRAM is referred to as an embedded DRAM...

AI Technical Summary

Benefits of technology

This approach enables the simultaneous enhancement of memory and logic device performance, maintaining the reliability of the gate insulating layer and current drive capability, while simplifying the manufacturing process by allowing for different thicknesses and materials in the gate electrodes, thus overcoming the trade-off between performance and complexity.

Problems solved by technology

On the other hand, if scheming to simplify the manufacturing processes by making common the processes for manufacturing the plurality of device FETs having the structures different from each other, it is difficult to obtain functions and performances demanded of the respective FETs.

It is therefore difficult to obtain a reliability of a gate insulating layer of the memory device FET, attain a speed-up of the logic device FET and reduce a manufacturing cycle time at the same time.

Germanium contained in poly-SiGe, however, diffuses over the gate insulating layer, thereby exerting an adverse influence upon a quality of the gate insulating layer, e.g., an interface trap density and a fixed charge density.

If the quality of the gate insulating layer is deteriorated, there decreases the time for the memory device FET to retain the electric charges.

Namely, there arises a problem in which a memory device FET's capability of retaining the electric charges declines because of using poly-SiGe for the gate electrode.

If the gate insulating layer of the memory device FET is too thin, the electric charges conduct by direct tunneling) the gate insulating layer, and consequently the electric charge retention capability declines.

This leads to deterioration of a retention time of the memory device FET.

It is, however, impossible to provide the gate insulating layers each having a different thickness on the same semiconductor substrate in the same process.

When the mask layer is provided on the gate insulating layer, however, a quality of the gate insulating layer declines due to a stress and contamination that are given to the gate insulating layer from the mask layer.

If the quality of the memory gate insulating layer declines, the electric charge retention capability decreases, which leads to the deterioration of the retention time of the memory device FET.

Further, the electric charges are trapped by a defect in the gate insulating layer, and the device function as a memory is degraded.

Accordingly, a problem is that the process of providing the logic gate insulating layer changes the thickness of the memory gate insulating layer.

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