Methods and apparatuses for thread management of mult-threading

a multi-threading and thread technology, applied in multi-programming arrangements, instruments, computing, etc., can solve the problems of memory latency becoming the critical bottleneck to achieving high performance on modern processors, many large applications today are memory intensive, and memory bottleneck problems still persis

Inactive Publication Date: 2005-03-31
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Memory latency has become the critical bottleneck to achieving high performance on modern processors.
Many large applications today are memory intensive, because their memory access patterns are difficult to predict and their working sets are becoming quite large.
Despite continued advances in cache design and new developments in prefetching techniques, the memory bottleneck problem still persists.
This problem worsens when executing pointer-intensive applications, which tend to defy conventional stride-based prefetching techniques.
However, SMT does not directly improve the performance, in terms of reducing latency, of single-threaded applications.
In addition, the current compiler typically cannot automatically allocate resources for the threads it created.

Method used

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  • Methods and apparatuses for thread management of mult-threading
  • Methods and apparatuses for thread management of mult-threading
  • Methods and apparatuses for thread management of mult-threading

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Embodiment Construction

Methods and apparatuses for compiler-creating helper threads for multi-threading systems are described. According to one embodiment, a compiler, also referred to as AutoHelper, that implements thread-based prefetching helper threads on a multi-threading system, such as, for example, the Intel Pentium™ 4 Hyper-Threading systems, available from Intel Corporation. In one embodiment, the compiler automates the generation of helper threads for Hyper-Threading processors. The techniques focus at identifying and generating helper threads of minimal sizes that can be executed to achieve timely and effective data prefetching, while incurring minimal communication overhead. A runtime system is also implemented to efficiently manage the helper threads and the synchronization between threads. Consequently, helper threads are able to issue timely prefetches for the sequential pointer-intensive applications.

In addition, hardware resources such as register contexts may be managed for helper thr...

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Abstract

Methods and apparatuses for thread management for multi-threading are described herein. In one embodiment, exemplary process includes selecting, during a compilation of code having one or more threads executable in a data processing system, a current thread having a most bottom order, determining resources allocated to one or more child threads spawned from the current thread, and allocating resources for the current thread in consideration of the resources allocated to the current thread's one or more child threads to avoid resource conflicts between the current thread and its one or more child threads. Other methods and apparatuses are also described.

Description

FIELD Embodiments of the invention relate to information processing system; and more specifically, to thread management for multi-threading. BACKGROUND Memory latency has become the critical bottleneck to achieving high performance on modern processors. Many large applications today are memory intensive, because their memory access patterns are difficult to predict and their working sets are becoming quite large. Despite continued advances in cache design and new developments in prefetching techniques, the memory bottleneck problem still persists. This problem worsens when executing pointer-intensive applications, which tend to defy conventional stride-based prefetching techniques. One solution is to overlap memory stalls in one program with the execution of useful instructions from another program, thus effectively improving system performance in terms of overall throughput. Improving throughput of multitasking workloads on a single processor has been the primary motivation behi...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F9/45G06F9/46
CPCG06F8/441
Inventor HOFLEHNER, GEROLF F.LIAO, SHIH-WEITIAN, XINMINWANG, HONGLAVERY, DANIEL M.WANG, PERRYKIM, DONGKEUNGIRKAR, MILINDSHEN, JOHN P.
Owner INTEL CORP
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