Methods and apparatuses for thread management of mult-threading

Abstract

Methods and apparatuses for thread management for multi-threading are described herein. In one embodiment, exemplary process includes selecting, during a compilation of code having one or more threads executable in a data processing system, a current thread having a most bottom order, determining resources allocated to one or more child threads spawned from the current thread, and allocating resources for the current thread in consideration of the resources allocated to the current thread's one or more child threads to avoid resource conflicts between the current thread and its one or more child threads. Other methods and apparatuses are also described.

Description

FIELD Embodiments of the invention relate to information processing system; and more specifically, to thread management for multi-threading. BACKGROUND Memory latency has become the critical bottleneck to achieving high performance on modern processors. Many large applications today are memory intensive, because their memory access patterns are difficult to predict and their working sets are becoming quite large. Despite continued advances in cache design and new developments in prefetching techniques, the memory bottleneck problem still persists. This problem worsens when executing pointer-intensive applications, which tend to defy conventional stride-based prefetching techniques. One solution is to overlap memory stalls in one program with the execution of useful instructions from another program, thus effectively improving system performance in terms of overall throughput. Improving throughput of multitasking workloads on a single processor has been the primary motivation behi...

AI Technical Summary

Benefits of technology

One solution is to overlap memory stalls in one program with the execution of useful instructions from another program, thus effectively improving system performance in terms of overall throughput. Improving throughput of multitasking workloads on a single processor has been the primary motivation behind the emerging simultaneous multithreading (SMT) techniques. An SMT processor can issue instructions from multiple hardware contexts, or logical processors (also referred to as hardware threads), to the functional units of a super-scalar processor in the same cycle. SMT achieves higher overall throughput by increasing overall instruction-level parallelism available to the architecture via the exploitation of the natural parallelism between independent threads during each cycle.

Problems solved by technology

Memory latency has become the critical bottleneck to achieving high performance on modern processors.

Many large applications today are memory intensive, because their memory access patterns are difficult to predict and their working sets are becoming quite large.

Despite continued advances in cache design and new developments in prefetching techniques, the memory bottleneck problem still persists.

This problem worsens when executing pointer-intensive applications, which tend to defy conventional stride-based prefetching techniques.

However, SMT does not directly improve the performance, in terms of reducing latency, of single-threaded applications.

In addition, the current compiler typically cannot automatically allocate resources for the threads it created.

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