MIS semiconductor device and method of fabricating the same

Abstract

A MIS type semiconductor device comprises a semiconductor layer provided with a recess portion having a side wall with an obtuse angle at least at a portion of the recess portion, a gate electrode formed over a bottom surface of the recess portion, with a gate insulating film interposed, a source region and a drain region formed on sides of the gate electrode with an insulating film interposed, such that boundary planes between the source region and the drain region, on one hand, and the insulating film, on the other hand, are formed in the semiconductor layer at an angle to a surface of the semiconductor layer, and wiring portions for contact with the surface of the semiconductor layer. Wherein an edge of the gate electrode is located inside the recess portion provided in the semiconductor layer, and there is provided at least one of a mutually opposed portion between the gate electrode and the source region and a mutually opposed portion between the gate electrode and the drain region, whereby at least one of a portion of the source region and a portion of the drain region, which lie in the associated mutually opposed portions, functions as an accumulation layer.

Description

BACKGROUND OF THE INVENTION [0001] The present invention relates generally to a MIS semiconductor device and a method of fabricating the same, and more particularly to improvements of a source region and a drain region. [0002] In order to meet a demand for a higher performance based on a higher integration density achieved by modern finer processing, when semiconductor integrated circuits (ICs) are fabricated, a gate electrode of a transistor is processed with a highest possible level of lithographic processing. Because of this, a variance occurs among gate electrodes and it leads to a variance in channel length and thus to a greater variance in transistor characteristics. Consequently, the product yield decreases. On the other hand, with miniaturization of semiconductor ICs, fine transistors and wiring are arranged very dense and the length of wiring increases. Even if the operation speed of transistors is to be increased based on the miniaturization, this cannot be achieved due to...

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Benefits of technology

[0033] The present invention has been made in consideration of the above problems, and its object is to provide a semiconductor device and a m

Problems solved by technology

Because of this, a variance occurs among gate electrodes and it leads to a variance in channel length and thus to a greater variance in transistor characteristics.

On the other hand, with miniaturization of semiconductor ICs, fine transistors and wiring are arranged very dense and the length of wiring increases.

Even if the operation speed of transistors is to be increased based on the miniaturization, this cannot be achieved due to a parasitic capacitance and resistance between transistors and wiring.

This contradicts the purpose of suppressing the short-channel effect.

Consequently, a large parasitic capacitance occurs.

However, since this transistor structure is of the flat type, the short-channel effect cannot fully be suppressed merely by controlling the thickness of the shallow diffusion layer 55a, 55b.

As has been described above, when the conventional semiconductor apparatus is used, it is not possible to suppress the short-channel effect, to reduce the parasitic capacitance or resistance, or to decrease the resistance of the current path.

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