System and method for arbitration of a plurality of processing modules

Abstract

Method and apparatus for an arbitrated high speed control data bus system providing high speed communications between microprocessor modules in a complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO queuing, TTL CMOS compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The system includes a parallel data bus with sharing bus masters residing on each processing module decreeing the communication and data transfer protocol. Bur arbitration is performed over a dedicated, independent, serial arbitration line. Each requesting module competes for access to the parallel data bus by placing the address of the requesting module on the arbitration line and monitoring the arbitration line for collisions, eliminating the need for both bus request and bus grant signals.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. patent application Ser. No. 10 / 166,216 filed on Jun. 10, 2002; which is a continuation of U.S. patent application Ser. No. 09 / 079,600, filed on May 15, 1998, which issued on Jun. 11, 2002 as U.S. Pat. No. 6,405,272; which is a continuation of U.S. patent application Ser. No. 08 / 671,221, filed on Jun. 27, 1996, which issued on May 19, 1998 as U.S. Pat. No. 5,754,803, all of which are incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates generally to a system for transferring data between a data processing module and a plurality of data processing modules. More particularly, the invention relates to a high-speed data communication system which transfers information between different digital processing modules on a shared parallel bus. [0004] 2. Description of the Related Art [0005] For communication within a digital device, suc...

AI Technical Summary

Benefits of technology

[0017] Method and apparatus for an arbitrated high speed control data bus system is provided which allows high speed communication between microprocessor modules in a more complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO (first-in / first-out) queing, TTL CMOS (complimentary metal-oxide silicon) compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The present invention includes a parallel data bus with sharing bus masters residing on each processing module controlling the communication and data transfer protocols. The high-speed intermodule communication bus (HSB) provides between various microprocessor modules. The data bus is synchronous and completely bidirectional. Each processing module that communicates on the bus will have the described bus control architecture. The HSB comprises, in one embodiment, eight shared parallel data lines for the exchange of digital data, and two independent lines for arbitration and clock signals. The need for explicit bus request or grant signals is eliminated. The HSB can also be configured as a semi-redundant system, duplicating data lines while maintaining a single component level. The bus is driven by three-state gates with resistor pullups serving as terminators to minimize signal reflections.

[0018] To move data on the HSB, each processing module specifies the data, the recipient, and the moment when the data is valid. Only one message source, known as the bus master, is allowed to drive the bus at any given time. Since the data flow is bidirectional, the bus arbitration scheme establishes a protocol of rules to prevent collisions on the data lines when a given processing module microprocessor is executing instructions. The arbitration method depends on the detection of collisions present only on the arbitration bus and uses state machines on each data processing module to determine bus status. Additionally, the arbitration method is not daisy chained, allowing greater system flexibility. The state machines located on each processing module are the controlling interface between the microprocessor used within a given processing module and the HSB. The circuitry required for the interface is comprised of a transmit FIFO, receive FIFO, miscellaneous directional / bidirectional signal buffers and the software code for the state machines executed in an EPLD (erasable programmable logic device).

Problems solved by technology

However, there must be some external logic ensuring that the three-state devices sharing the same lines do not talk at the same time or bus contention will result.

More complex bus systems permit other devices located on the bus to master the bus.

However, the device sending the data does not know if the data was received.

In an asynchronous bus, although handshaking between communicating devices assures the sending device that the data was received, the hardware and signaling complexity is increased.

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