Wafer acceptance testing method and structure of a test key used in the method

Abstract

A wafer acceptance testing (WAT) method for monitoring GC-DT misalignment and a test key structure are disclosed. The test key includes a deep trench capacitor structure biased to a first voltage (VDT). The deep trench capacitor structure is formed in a substrate, on which active areas are defined. The deep trench capacitor structure includes a buried strap out diffusion region that is formed within the active area and is electrically connected to the deep trench capacitor structure. The deep trench capacitor structure is isolated by shallow trench isolation (STI). A GC-T electrode layout and a GC-B electrode layout are formed over the substrate. The GC-T electrode layout, which is biased to a second voltage (VGC-T), includes a plurality of columns of GC-T fingers. The GC-B electrode layout, which is biased to a third voltage (VGC-B), includes a plurality of columns of GC-B fingers that interdigitate the plurality of columns of GC-T fingers over the active areas and STI. A first capacitance C1 of a first capacitor contributed by the plurality of columns of GC-T fingers and the buried strap out diffusion region is measured. A second capacitance C2 of a second capacitor contributed by the plurality of columns of GC-B fingers and the buried strap out diffusion region is measured. The first capacitance C1 and second capacitance C2 are compared, wherein when C1≠C2, GC-DT is misaligned.

Description

BACKGROUND OF INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a wafer acceptance testing (WAT) method, and more particularly, to a WAT method for monitoring gate conductor-deep trench (GC-DT) misalignment and a test key structure used in this method. [0003] 2. Description of the Prior Art [0004] In semiconductor fabrication, a semiconductor device or an integrated circuit (IC) should be continuously tested in every step so as to maintain device quality. Usually, a testing circuit is simultaneously fabricated with an actual device so that quality of the actual device can be judged by a performance of the testing circuit. The quality of the actual device therefore can be well controlled. Typically, such testing circuit, which is also referred to as “test key”, is disposed on peripheral area of each chip or die. [0005] Please refer to FIG. 1 and FIG. 2. FIG. 1 is an enlarged top view of a part of a conventional test key layout for monitoring GC-DT (Ga...

AI Technical Summary

Benefits of technology

The present invention provides a novel method for testing the alignment of gate conductor-deep trench (GC-DT) in a wafer. This method involves using a test key structure that includes a deep trench capacitor structure embedded in a substrate. The test key structure is connected to an out diffusion in an active area of the substrate. The deep trench capacitor structure has interdigitated GC-T electrode layout and GC-B electrode layout. The capacitance of two capacitors is measured, and the results are compared to determine if there is misalignment between the two layers. This method provides a reliable and accurate way to monitor GC-DT misalignment.

Problems solved by technology

However, the prior art GC-DT misalignment evaluation method is not accurate because there are so many factors affecting the threshold voltages shift of the GC-T 201 and GC-B 204.

Therefore, it is difficult for an inspector to judge the GC-DT misalignment merely according to the measured threshold voltage shift data.

Images