Bandwidth-adaptive, hybrid, cache-coherence protocol

Abstract

A cache coordination mechanism for a multiprocessor, shared-memory computer switches between a snooping mechanism where an individual processor unit broadcasts or multicasts cache coherence messages to each other node on the system and a directory system where the individual processor unit transmits the cache control message to a directory which then identifies potential candidates to receive that message. The switching is according to the activity on the communication network used by the cache coherence messages. When network activity is high, a directory protocol is used to conserve bandwidth but when network activity is low, a snooping system is used to provide faster response.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of U.S. patent application Ser. No. 10 / 037,727, filed Oct. 19, 2001, which claims the benefit of Provisional Application No. 60 / 275,743, filed Mar. 14, 2001.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT [0002] This invention was made with United States government support awarded by the following agencies: [0003] NSF 9971256 [0004] The United States has certain rights in this invention. BACKGROUND OF THE INVENTION [0005] The present invention relates generally to a system for coordinating cache memories in a shared-memory computer architecture, and in particular, to a system that chooses a mechanism for communicating cache coherence messages based on the bandwidth available for transmitting such messages. [0006] Large computer software applications, such as simulators and database servers, require cost-effective computation beyond that which can be provided by a single microprocessor. Sh...

AI Technical Summary

Benefits of technology

The present invention provides an adaptive, hybrid protocol for communicating cache coherence messages in a multiprocessor computer system. The protocol adapts to the available bandwidth by selectively using snooping or a directory mechanism based on the evaluation of the available bandwidth. The protocol includes a method and apparatus for coordinating cache memories in a multiprocessor computer system, which can communicate cache coherence messages over a network. The invention streamlines the directory process over the process normally used in multicast snooping, and addresses possible problems of live lock and ambiguity at the receiving node. The evaluation of available bandwidth may compare it against a predetermine threshold and select between snooping and directory mechanisms accordingly. The invention provides improved control dynamics and lower latency correction mechanisms for speculatively multicasting.

Problems solved by technology

Generally, such protocols invalidate all other cache memories when one cache is written to, and updating of the main memory before a changed cache is flushed.

For large systems with many processors, however, snooping generates large numbers of messages which may overwhelm a communications channel.

While the above principals guide the system designer in selecting between snooping and directory protocols, the decision can be complicated.

Selecting one of a directory protocol or a snooping protocol will result in less than optimal performance when the same system is configured with different numbers of processors or in certain upgrade operations where more processors are added to the system.

Second, even for a fixed number of processors, the application being executed may result in a radically different demand on the cache protocol communication network for which one of the snooping or directory protocols will be preferable to the other protocol.

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