Delay library generation method and delay library generation device

Abstract

A delay library of high accuracy is efficiently generated within a short time period. To this end, a set-up time is calculated by static analysis with no consideration of a delay caused by a wire; the initial value of the search range for the next binary search cycle is set such that the set-up time is the median value of the search range (for example, the range of 0.5 ns is set); and correct set-up time α is obtained using binary search based on the initial value of the search range.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This Nonprovisional application claims priority under 35 U.S.C. §119 (a) on Patent Application No.2003-435316 filed in Japan on Dec. 26, 2003, the entire contents of which are hereby incorporated by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a method and device for generating a delay library including a timing constraint value and a delay value, which is used for verifying the operation timing of a semiconductor integrated circuit. [0004] 2. Description of the Prior Art [0005] The operation timing of a semiconductor integrated circuit is verified using a delay library which includes information about circuit characteristics of each of logic circuits (logic cells) which constitute the semiconductor integrated circuit, such as a timing constraint value, a delay value, and the like. The delay library is generated by extracting the characteristics of each cell with a device...

AI Technical Summary

Benefits of technology

[0013] In view of the above, an objective of the present invention is to efficiently generate a delay library of high accuracy within a short time period.

[0014] In order to achieve the above objective, according to the present invention, in the process of obtaining a timing constraint value of a logic circuit using a simulation of circuit operation and a binary search method, the timing constraint value is first obtained with an accuracy lower than a target accuracy, such that the initial value of the search range of the binary search method is set small (i.e., the initial search range of the binary search method is set narrow). Accordingly, the number of simulation cycles is decreased. As a result, a delay library of high accuracy is efficiently generated within a short time period.

[0016] In the case where the timing constraint values are obtained for a plurality of logic circuits of the same type or a plurality of logic circuits which include a common circuit element, the timing constraint value obtained for any one of the logic circuits is used as the initial value of the timing constraint value in the binary search process for obtaining the timing constraint values of the other logic circuits. Also with this structure, the initial value of the search range can readily be set small (i.e., the initial search range can readily be set narrow).

[0017] A timing constraint value having a certain degree of accuracy is obtained for a simplified circuit model, and the obtained timing constraint value is used as the initial value in the process of obtaining a timing constraint value for a detailed circuit model. Also with this structure, the initial value of the search range can readily be set small (i.e., the initial search range can readily be set narrow).

[0018] In the case of obtaining a plurality of timing constraint values according to the variation rate of an input signal, for example, a timing constraint value corresponding to a predetermined variation rate is first obtained, and a value calculated by interpolation or extrapolation using the obtained timing constraint value is used as the initial value in the process of obtaining a timing constraint value corresponding to a different variation rate. Also with this structure, the initial value of the search range can readily be set small (i.e., the initial search range can readily be set narrow).

[0019] It is possible that, for example, the above simulation is performed with different accuracies for signal transmission paths corresponding to (associated with) the timing constraint values or delay times to be obtained, whereby the time required for generating a delay library is further reduced.

Problems solved by technology

As a result, the delay time caused by wires has been increasing.

However, the above conventional method requires a long time for obtaining the timing constraint value.

In the case where the timing constraint value is obtained using a binary search method, it is in general difficult to predict a range including the timing constraint value.

As a result, a long time is required before the predicted value converges.

As a result, a considerable length of time is required.

Thus, it is difficult to predict the timing constraint value, for example, with the accuracy range of about 0.5 ns for setting the initial value of the search range.

However, the amount of calculations increases, and accordingly, the time required for one simulation cycle increases.

Thus, the above problems become more noticeable.

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