Method of manufacturing a semiconductor device having trenches for isolation and capacitor
a manufacturing method and semiconductor technology, applied in the field of manufacturing semiconductor devices, can solve the problems of unfavor undesirable increase in manufacturing steps for respectively forming them, and achieve the effects of improving capacitor capacitance per unit area, increasing capacitor surface area, and increasing capacitor surface area
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embodiment 1
[0096]FIG. 1 shows a plan view of the basic parts of a semiconductor device having a nonvolatile memory, which represents one embodiment of the present invention. FIG. 1 shows the plan view of a memory cell of the nonvolatile memory on the left-hand side, a MISFET at the central part, and a capacitor (capacitive element) on the right-hand side. FIG. 2 shows cross sectional diagrams of the memory cell on the left-hand side, a MISFET for high voltage (a high-voltage MISFET) at the central part, and a capacitor on the right-hand side, which correspond to cross sectional diagrams taken along the lines A-A′, B-B′, and C-C′ of FIG. 1, respectively. The capacitor shown in FIG. 2 uses a gate insulating film of the high-voltage MISFET as its dielectric film.
[0097]FIG. 3 shows the respective cross sectional diagrams of a MISFET for low voltage (a low-voltage MISFET) on the left-hand side and a capacitor on the right-hand side, which are the cross sectional diagrams taken along B-B′ and C-C′ ...
embodiment 2
[0163] The configuration of the essential parts of a semiconductor device of embodiment 2 of the present invention is shown in FIG. 25.
[0164] In the foregoing embodiment 1, as shown in FIG. 9, in the step of removing the silicon oxide film 5 that is embedded in the capacitor formation trenches 4a, the mask as shown in FIG. 14 was used as a resist pattern. However, in this embodiment 2, a part of the element isolation trench 4 may also be used as a part of the capacitor formation region by performing patterning by using the mask shown in FIGS. 27 and 28.
[0165] Incidentally, for convenience in the description, a description of the same part in the following process as was used in the foregoing embodiment 1 will be omitted.
[0166] First, after the step shown in FIG. 12 in the foregoing embodiment 1, a is resist pattern 125, as shown in FIGS. 27 and 28, is formed on the silicon oxide film 5, that is embedded in the element isolation trench 4 (see FIG. 12), and in at least not less tha...
embodiment 3
[0171] The configuration of the essential parts of a semiconductor device of embodiment 3 of the present invention is shown in FIG. 29.
[0172] In the foregoing embodiment 1, the step of forming the gate insulating films (the low-voltage gate insulating film 15 and the high-voltage gate insulating film 16) of the MISFETs was the same step as the step of forming the dielectric film 15a or 16a of the capacitor. However, in this embodiment 3, the NONO film 11, which is the memory gate interlayer film (second memory gate insulating film) of the memory cell and the capacitor dielectric film of the capacitor, are formed of the dielectric film of the same layer. Namely, the step of forming the NONO film 11, which is the memory gate interlayer film (second memory gate insulating film) of the memory cell, and the step of forming the capacitor dielectric film of the capacitor are set to be the same.
[0173] Incidentally, for convenience in the description, a description of the same part in the ...
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