Low voltage semiconductor memory device

Abstract

A semiconductor memory device having a cell array area for reading or storing data, including: a normal cell block including a plurality of normal cells, each being coupled to one of a bit line and a bit line bar for storing a data; and a reference cell block including a plurality of reference cell units, each including a reference capacitor, a first reference transistor for connecting a first terminal of the reference capacitor to the bit line, a second reference transistor for connecting the first terminal of the reference capacitor to the bit line bar, and a third reference transistor connected to a reference voltage for supplying the reference voltage to the first terminal of the reference capacitor.

Description

FIELD OF INVENTION [0001] The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device capable of efficiently operating at a low voltage. DESCRIPTION OF PRIOR ART [0002]FIG. 1 is a block diagram of a conventional semiconductor memory device. [0003] Referring to FIG. 1, the conventional semiconductor memory includes a row address input unit 20 for decoding a row address, a column address input unit 30 for decoding a column address, a cell area 100 provided with a plurality of cell arrays 110, 120, 130 and 140 each having a plurality of unit cells, for outputting data corresponding to the output signals of the row address input unit 20 and the column address input unit 30, and a data input / output unit 40 for outputting the output data of the cell area 100 to an outside or transferring an external data to the cell area. [0004] The cell area 100 includes sense amplifiers 150 and 160 for amplifying data signals from the cell arr...

AI Technical Summary

Benefits of technology

[0065] It is, therefore, an object of the present invention to provide a semiconductor memory device capable of operating at a high speed even at a low voltage and preventing an occurrence of a bleed current, thereby reducing a wasteful power consumption. In particular, there is provided a layout of the semiconductor memory device.

Problems solved by technology

However, even though the level of the power supply voltage is lowered, the semiconductor memory device is required to maintain or increase the operating speed.

However, it is difficult to reduce the manufacturing technology in 100 nm or less.

Also, the required power supply voltage is reduced to 2.0 V or 1.5 V, and even 1.0 V. Under such a situation, it is difficult to maintain the required operating speed only by reducing the manufacturing technology.

In addition, if the power supply voltage supplied to the semiconductor memory device is lowered below a predetermined level, an operating margin of the MOS transistors configuring the semiconductor memory device becomes very small.

Therefore, the semiconductor memory device cannot operate according to the required operating speed and cannot rely on the stable operation.

In such a situation that the turn-on voltage of the MOS transistor maintains a predetermined level, if the level of the driving voltage inputted to the semiconductor memory device is lowered below a predetermined level, it takes a long time for the sense amplifier to sense and amplify a voltage difference between two bit lines.

At this point, even though noise occurs slightly (that is, the bit line voltage level rises or falls due to a slight noise at the ½ core voltage), the sense amplifier may not operate correctly.

Accordingly, it is difficult to reduce the driving voltage for the semiconductor memory device below a predetermined level.

Also, if the manufacturing technology is reduced very much, a gap between a gate electrode of a MOS transistor in each unit cell and bit lines arranged adjacent to the gate electrode becomes very narrow, so that leakage current flows between the gate electrode and the bit lines.

Thus, a sufficient insulation is difficult.

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