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Latch-based pulse generator

a pulse generator and latch technology, applied in the field of latch-based pulse generators, can solve problems such as excessive power consumption, and achieve the effect of reducing power consumption and reducing the number of transistors

Inactive Publication Date: 2006-06-29
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This design significantly reduces power consumption by minimizing the number of transistors that toggle in response to clock signals, while maintaining the functionality of generating pulses for data latching in TFT-LCD drivers.

Problems solved by technology

Therefore, the output of one pulse generator (e.g., the pulse generator 100_n) toggles a minimum of 127 times to generate a pulse L_CLKn, resulting in excess power consumption.

Method used

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  • Latch-based pulse generator
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  • Latch-based pulse generator

Examples

Experimental program
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Embodiment Construction

[0035]FIG. 4 is a circuit diagram of a latch-based pulse generator 400 according to an exemplary embodiment of the present invention. Referring to FIG. 4, the pulse generator 400 includes first, second and third input terminals 481, 482, 483 and first, second and third output terminals 491, 492, 493.

[0036] A first NAND gate 401 receives and NANDs an input signal SFT_IN input to the second input terminal 482 and an input signal SFTR_IN input via the third input terminal 483, and outputs the result of the NAND operation to a first inverter 403.

[0037] The level of the input signal SFTR_IN input to the third input terminal 483 is changed from a logic high level to a logic low level over a predetermined length of time after the level of the input signal SFT_IN input to the second input terminal 482 is changed from a logic low level to a logic high level.

[0038] The first inverter 403 receives and inverts the signal output from the first NAND gate 401 and outputs an inverted signal enb ...

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Abstract

There is provided a pulse generator capable of generating a pulse with a reduced number of transistors that toggle in response to a clock signal, thereby reducing power consumption. The pulse generator includes a plurality of unit cells, wherein an nth unit cell (n is a natural number more than 2) generates a pulse in response to a divided-by-N clock signal (N is a natural number), a signal output from an (n−1)th unit cell and a signal output from an (n+1)th unit cell. The nth unit cell is reset or generates the pulse whose width is equivalent to the width of the clock signal, according to the logic level of the signal output from the n+1th unit cell.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a Divisional of U.S. application Ser. No. 10 / 774,680 filed on Feb. 9, 2004, which claims priority to Korean Patent Application No. 2003-10050, filed on Feb. 18, 2003.BACKGROUND OF THE INVENTION [0002] 1. Technical Field [0003] The present invention relates to a pulse generator, and more particularly, to a latch-based pulse generator, which is used in an active matrix type thin film transistor liquid crystal display (TFT-LCD) driver. [0004] 2. Discussion of the Related Art [0005]FIG. 1 is a circuit diagram of a common pulse generator 100. Referring to FIG. 1, the pulse generator 100 includes inverters 120 and 140, a flip-flop 110, and a NAND gate 130. As shown in FIG. 1, the inverters 120 and 140 (i.e., complementary metal oxide semiconductor (CMOS) inverters) include positive channel metal oxide semiconductor (PMOS) and negative channel metal oxide semiconductor (NMOS) transistors. The NAND gate 130 also includes two...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F1/04G11C19/00H03K3/00H03K3/353H03K3/037H03K5/05
CPCG11C19/00H03K5/05H03K3/037H03K3/353
Inventor KIM, DO-KYUNGJEON, YONG-WEON
Owner SAMSUNG ELECTRONICS CO LTD