Latch-based pulse generator
a pulse generator and latch technology, applied in the field of latch-based pulse generators, can solve problems such as excessive power consumption, and achieve the effect of reducing power consumption and reducing the number of transistors
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[0035]FIG. 4 is a circuit diagram of a latch-based pulse generator 400 according to an exemplary embodiment of the present invention. Referring to FIG. 4, the pulse generator 400 includes first, second and third input terminals 481, 482, 483 and first, second and third output terminals 491, 492, 493.
[0036] A first NAND gate 401 receives and NANDs an input signal SFT_IN input to the second input terminal 482 and an input signal SFTR_IN input via the third input terminal 483, and outputs the result of the NAND operation to a first inverter 403.
[0037] The level of the input signal SFTR_IN input to the third input terminal 483 is changed from a logic high level to a logic low level over a predetermined length of time after the level of the input signal SFT_IN input to the second input terminal 482 is changed from a logic low level to a logic high level.
[0038] The first inverter 403 receives and inverts the signal output from the first NAND gate 401 and outputs an inverted signal enb ...
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