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Semiconductor device and method for manufacturing semiconductor device

Inactive Publication Date: 2006-07-27
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0035] An object of the present invention is to provide a semiconductor device having side wall spacers made of insulating films having a barrier function and being free of disadvantages to be caused by forming the side wall spacers.
[0036] Another object of the present invention is to provide a semiconductor device integrating flash memory cells, low voltage operation transistors and high voltage operation transistors and being free of disadvantages to be caused by mixedly forming different types of transistors.

Problems solved by technology

As the pn junction depth of source / drain regions becomes shallow, resistance values have a tendency of becoming large.
Damages are therefore hard to be formed in the surface layer of the active regions.
If metal enters the undercuts in a later process and left unremoved, the remaining metal may cause a short circuit.
However, since the nitride film side wall spacers contact the substrate surfaces, it is inevitable that the nitride film side wall spacers impart stresses to the substrate.
While the gate electrode pattern is dry-etched, if the gate insulating film is also removed, the substrate surface is exposed to etching and may be damaged.
As the extension regions are subjected to the heat treatment at 700° C. or higher, impurities are thermally diffused so that there is a possibility that the extension regions cannot retain a desired shape.
As the overhangs are formed, the overhangs may cause a short circuit and the like.
As above, as semiconductor elements of a plurality of types are formed on the same semiconductor substrate and the characteristics of each semiconductor element are to be optimized, unexpected disadvantages may be given to other semiconductor devices.

Method used

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  • Semiconductor device and method for manufacturing semiconductor device
  • Semiconductor device and method for manufacturing semiconductor device
  • Semiconductor device and method for manufacturing semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0048] Embodiments of the present invention will be described with reference to the drawings. FIGS. 1A to 1E are cross sectional views schematically illustrating a manufacture method for a semiconductor device according to the present invention.

[0049] As shown in FIG. 1A, an isolation trench is formed in the surface layer of, e.g., a p-type semiconductor substrate 11, an insulating film is buried in the trench, and an unnecessary portion of the insulating film is removed by chemical mechanical polishing (CMP) to form an STI type isolation region 12. The surface of each active region defined by the isolation region 12 is thermally oxidized at 800° C. to 1100° C. to form a gate insulating film 13. A polysilicon film is deposited on the surface of the semiconductor substrate, covering the gate oxide film 13. By using a photoresist pattern as a mask, the polysilicon film is etched to pattern a gate electrode 14.

[0050] In this case, mixture gas of HBr and Cl2 is used as etching gas to p...

second embodiment

[0057]FIGS. 2A to 2E are cross sectional views schematically illustrating a semiconductor device manufacture method according to the present invention.

[0058]FIGS. 2A and 2B show the same structures as those shown in FIGS. 1A and 1B, and these structures can be manufactured by the same processes.

[0059] As shown in FIG. 2C, side wall spacers 23 of TEOS silicon oxide are formed covering the side wall spacers 16 of silicon nitride. The TEOS silicon oxide film has an etching rate faster than that of the thermally oxidized film. While the side wall spacers 23 are formed, control etching is performed to leave the gate oxide film 13.

[0060] As shown in FIG. 2D, for a silicidation reaction, the surfaces of the substrate 11 and gate electrode 14 are exposed by using dilute hydrofluoric acid solution. In this etching, the TEOS silicon oxide film 23 has an etching rate faster than that of the thermally oxidized gate oxide film 13. Therefore, when the gate oxide film 13 and TEOS silicon oxide f...

third embodiment

[0063]FIGS. 3A to 3E are cross sectional views schematically illustrating a semiconductor device manufacture method according to the present invention.

[0064]FIG. 3A shows the same structure as that shown in FIG. 1A, and this structure can be manufactured by the same process.

[0065] As shown in FIG. 3B, a silicon oxide film made of TEOS and a silicon nitride film are successively deposited covering the gate electrode 14, etched back to form laminated side wall spacers made of silicon oxide films 24 covering the side walls of the gate electrode 14 and silicon nitride films 16 on the silicon oxide films 24. Instead of the TEOS silicon oxide film, a silicon oxide film formed by thermal oxidation may be used. In forming the side wall spacers, the silicon nitride film is etched by using mainly CHF3 gas as etching gas, and the silicon oxide film is etched mainly by using CF4 gas as etching gas. If the gate oxide film 2 is to be left, control etching with limited time is performed.

[0066] A...

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PUM

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Abstract

A semiconductor device is provided which has insulating film side wall spacers having a barrier function. The semiconductor device comprises: a gate oxide film and a gate electrode formed on and above a semiconductor substrate; source / drain regions formed in the semiconductor substrate; and first laminated side wall spacers having two or more layers and formed on side walls of the gate electrode, the first laminated side wall spacers including a nitride film as a layer other than an outermost layer, the outermost layer being made of an oxide film or an oxynitride film and having a bottom surface contacting the semiconductor substrate, the gate oxide film or a side wall spacer layer other than the nitride film.

Description

CROSS REFERENCE TO RELATED APPLICATION [0001] This application is based on and claims priority of PCT / JP2003 / 013582 filed on Oct. 23, 2003, the entire contents of which are incorporated herein by reference.TECHNICAL FIELD [0002] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a highly integrated semiconductor device having side wall spacers with a barrier function and a method of manufacturing the semiconductor device. BACKGROUND ART [0003] Since self-aligned contacts (SAC) are used recent years because of micro patterning requirements, side wall spacers of silicon nitride film are used. A silicon nitride film is an insulating film with a barrier function capable of functioning as an etching stopper having etching selectivity relative to an interlayer insulating film made of a silicon oxide film. [0004] Device sizes are reduced due to high integration and miniaturization of MOSFETs. As the pn j...

Claims

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Application Information

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IPC IPC(8): H01L29/94H01L21/265H01L21/28H01L21/336H01L21/8234H01L21/8239H01L21/8247H01L27/105H01L29/78H01L29/788H01L29/792
CPCH01L21/2652H01L21/28273H01L21/28282H01L21/823456H01L21/823462H01L21/823468H01L27/105H01L27/115H01L27/11526H01L27/11546H01L27/11573H01L29/4983H01L29/665H01L29/6653H01L29/66545H01L29/6656H01L29/6659H01L29/66825H01L29/66833H01L29/7833H01L29/7881H01L29/792H01L27/1052H01L29/40114H01L29/40117H10B41/40H10B41/49H10B43/40H10B69/00H10B99/00
Inventor ANEZAKI, TORU
Owner FUJITSU LTD
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