Semiconductor device having a merged region and method of fabrication

Abstract

A semiconductor device includes an insulated gate electrode pattern formed on a well region. The semiconductor device further includes a sidewall spacer formed on sidewalls of the gate electrode pattern. A source region and a drain region are formed adjacent opposite sides of the gate pattern. In accordance with one embodiment of the present invention, one of the source or drain regions includes a first-concentration impurity region formed under the sidewall spacer. The semiconductor device further includes a silicide layer formed within the well region wherein at least a part of the silicide layer contacts a portion of the well region to bias the well region. A method of manufacturing the semiconductor device is also provided.

Description

[0001] This application is a Divisional of U.S. patent application Ser. No. 10 / 194,181, filed Jul. 12, 2002, now pending, which is incorporated by reference in its entirety.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates generally to semiconductor devices, and, more particularly, to a semiconductor device structure for well biasing to prevent latch-up or soft errors. [0004] 2. Description of Related Art [0005] Complementary metal-oxide semiconductor (CMOS) circuits such as CMOS static random access memory (SRAM) cells encounter problems such as latch-up or soft errors. [0006] In CMOS circuits, latch-up occurs due to the presence of complementary parasitic bipolar transistor structures. Because n-channel and p-channel devices are in close proximity to one other in CMOS circuits, inadvertent (parasitic) p-n-p-n bipolar structures can be found. As a result, under certain biasing conditions, the p-n-p part of the structure can supply base curre...

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor device with an insulated gate electrode pattern and a method for forming it. The device includes a sidewall spacer, a source region, and a drain region. The source region has a first-concentration impurity region and a silicide layer formed within the well region for biasing the well region. The invention merges a well-tie region with a source region, reducing cell sizes and increasing packing density without being limited by photolithography technology.

Problems solved by technology

Complementary metal-oxide semiconductor (CMOS) circuits such as CMOS static random access memory (SRAM) cells encounter problems such as latch-up or soft errors.

As a result, under certain biasing conditions, the p-n-p part of the structure can supply base current to the n-p-n structure, causing a large current to flow.

This can cause the circuit to malfunction, or even destroy the circuit itself due to heat caused by high power dissipation.

In addition to the problem of latch-up, if energetic particles from the environment, such as alpha-particles, strike a junction, such as the drain junction, surrounded by a depletion region, electrons and holes will be generated within the underlying body of the semiconductor material and will collect along the boundary of the depletion region.

If the charge perturbation is sufficiently large, the stored logic state may be reversed, causing a so called “soft error.” Latch-up and soft errors are both increased by the unstable potential of well stand-by operation at reduced voltage.

Unfortunately, this method requires a large area within the cell for forming a separated well-tie implant region 18 and separated contacts 28, 30, substantially decreasing packing density of an integrated circuit.

Also, conventional methods are limited due to precision limits inherent in the photolithography process used in forming these fine structures.

Images