Semiconductor device

a semiconductor and device technology, applied in the field of semiconductor devices, can solve the problems of affecting the character reducing the size of the semiconductor element, and displacing the semiconductor element under a pad and a bump,

Inactive Publication Date: 2007-01-11
SEIKO EPSON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0010] a bump formed in the opening and having a rectangular planar shape having a short side and a long side, the bump at least partially covering the element when viewed from a top sid

Problems solved by technology

In related-art technology, when disposing a semiconductor element such as a MOS transistor under a pad, the characteristics of the semiconductor element may be impaired due to stress during bo

Method used

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  • Semiconductor device
  • Semiconductor device
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first embodiment

1. First Embodiment

[0077]FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment of the invention, and FIG. 2 is a plan view schematically showing the relationship between the shape of an electrode pad and a forbidden region in the semiconductor device according to the first embodiment. FIG. 1 shows the cross section along the line X-X shown in FIG. 2.

[0078] As shown in FIG. 1, the semiconductor device according to the first embodiment includes a semiconductor layer 10. As the semiconductor layer 10, a single crystal silicon substrate, a silicon on insulator (SOI) substrate in which a semiconductor layer is formed on an insulating layer, the semiconductor layer being a silicon layer, a germanium layer, or a silicon germanium layer, or the like may be used.

[0079] An isolation insulating layer 20 is formed in the semiconductor layer 10. The isolation insulating layer 20 may be formed by a shallow trench isolation (STI) method, a ...

second embodiment

2. Second Embodiment

[0091] A second embodiment of the invention is described below with reference to FIG. 4. FIG. 4 is a cross-sectional view schematically showing a semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that a semiconductor element is formed in the forbidden region 12. The following description merely illustrates the difference from the semiconductor device according to the first embodiment.

[0092] As shown in FIG. 4, the semiconductor device according to the second embodiment includes the element formation region 10A and the forbidden region 12 provided around the element formation region 10A. In the semiconductor device according to the second embodiment, the element formation region 10B is provided outside the forbidden region 12 in the same manner as in the semiconductor device according to the first embodiment, although not s...

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PUM

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Abstract

A semiconductor device including: a semiconductor layer including an element formation region and an isolation region provided around the element formation region; an element formed in the element formation region; an interlayer dielectric formed above the semiconductor layer; an electrode pad formed above the interlayer dielectric; a passivation layer formed above the electrode pad and having an opening which exposes at least part of the electrode pad; and a bump formed in the opening and having a rectangular planar shape having a short side and a long side, the bump at least partially covering the element when viewed from a top side, and the semiconductor layer positioned within a specific range inward and outward from a line extending vertically downward from the short side of the bump being a forbidden region.

Description

[0001] Japanese Patent Application No. 2005-197927, filed on Jul. 6, 2005, and Japanese Patent Application No. 2006-74732, filed on Mar. 17, 2006, are hereby incorporated by reference in their entirety. BACKGROUND OF THE INVENTION [0002] The present invention relates to a semiconductor device. [0003] In related-art technology, when disposing a semiconductor element such as a MOS transistor under a pad, the characteristics of the semiconductor element may be impaired due to stress during bonding. Therefore, the pad formation region and the semiconductor element formation region are separately provided in a semiconductor chip when viewed from the top side. However, since the semiconductor chip has been reduced in size and increased in degree of integration, disposition of the semiconductor element under a pad and a bump has been in demand. JP-A-2002-319587 discloses such technology, for example. SUMMARY [0004] According to a first aspect of the invention, there is provided a semicondu...

Claims

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Application Information

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IPC IPC(8): H01L23/48
CPCH01L21/823475H01L21/823481H01L2924/13091H01L2924/01006H01L2924/01005H01L2924/00013H01L24/13H01L2924/19043H01L2924/01082H01L2924/01079H01L2924/01078H01L24/11H01L2224/0401H01L2224/05554H01L2224/1147H01L2224/13012H01L2224/13144H01L2224/13147H01L2224/13155H01L2924/01013H01L2924/01015H01L2924/01022H01L2924/01029H01L2924/01032H01L2924/01033H01L2924/01074H01L2924/00014H01L2224/13099H01L2924/00H01L24/05H01L2224/05124H01L2224/05147H01L2224/05166H01L2224/05624H01L2224/05644H01L2224/05647H01L2224/05666H01L2224/0615H01L2224/13013H01L2924/013H01L21/76H01L23/48
Inventor SHINDO, AKINORITAGAKI, MASATOSHIKURITA, HIDEAKI
Owner SEIKO EPSON CORP
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