Re-sampling methodology for wireless broadband system

Abstract

A system and method for performing a convolution operation in a multi-mode wireless processing system. The method can include loading an initial value and a stride value into an address generator, generating an address based on the initial value and the stride value, supplying the generated address to a series of memories, loading input data into a series of registers, multiplying the contents of each register with a value stored at the generated address in the memory associated with each register, adding up the resulting multiplication products, and generating output based on the resulting sum. The number of memories and registers are equal, each register having an associated memory.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is related to U.S. patent application No. ______ (Attorney Docket No. 023573-0801) entitled SYSTEM AND METHOD FOR SELECTIVELY OBTAINING PROCESSOR DIAGNOSTIC DATA, U.S. patent application No. ______ (Attorney Docket No. 023573-0901) entitled CONTROLLING INPUT AND OUTPUT IN A MULTI-MODE WIRELESS PROCESSING SYSTEM, U.S. patent application No. ______ (Attorney Docket No. 023573-1001) entitled DYNAMICALLY CONTROLLING RATE CONNECTIONS TO SAMPLE BUFFERS IN A MULTI-MODE WIRELESS PROCESSING SYSTEM, U.S. patent application No. ______ (Attorney Docket No. 023573-1101) entitled MULTI-MODE WIRELESS PROCESSOR INTERFACE, U.S. patent application No. ______ (Attorney Docket No. 023573-1201) entitled FAST FOURIER TRANSFORM (FFT) ARCHITECTURE IN A MULTI-MODE WIRELESS PROCESSING SYSTEM, and U.S. patent application No. ______, (Attorney Docket No. 023573-1301) entitled A METHOD FOR SWITCHING INSTRUCTION CONTEXTS IN A MULTI-MODE WIRELESS PRO...

AI Technical Summary

Benefits of technology

The patent text describes a method and system for performing a convolution operation in a multi-mode wireless processing system. The system includes an address generator, a series of memories, a series of registers, a series of complex multipliers, and a complex adder tree. The method involves loading an initial value and a stride value into the address generator, generating an address based on the initial value and the stride value, supplying the generated address to the memories, loading input data into the registers, multiplying the contents of each register with a value stored at the generated address in the associated memory, adding up the resulting multiplication products, and generating output based on the resulting sum. The technical effects of this patent text are improved performance and efficiency in performing convolution operations in a multi-mode wireless processing system.

Problems solved by technology

However, conventional 802.11 implementations fail to meet user-acceptable power consumption parameters.

Even the lowest power-consuming 802.11 implementations currently available severely limit “talk time” (active state during which voice, data, or video is being transferred) for battery operated devices.

Beyond devising an 802.11 implementation with acceptable power consumption, another challenge is to establish a wireless implementation that supports two or more networking modes of operation, such as 802.11, Bluetooth, Ultra Wideband (UWB), WiMax (802.16d and 802.16e), 802.20, and 3G and 4G cellular systems.

Several engineering considerations, such as power efficiency, design flexibility and cost, prevent either approach from being suitable for broadband wireless.

Because of architectural limitations, conventional approaches may be able to provide high data rates, but only at the expense of power consumption, resulting in an unacceptably short battery life.

With new wireless standards being introduced everyday, traditional ASIC design is too inflexible to continually accommodate these rapidly evolving standards.

Once the integrated circuit design cycle begins for a new standard, modifications that inevitably occur necessitate re-starting from scratch or re-spinning the ASIC chip.

To provide the multiple wireless capabilities end users demand on a single device, ASIC and DSP approaches support multi-mode capability by simply stacking additional “processing circuitry” in parallel, significantly increasing device volume and manufacturer costs for each new mode.

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