High density semiconductor memory and method of making
a high-density, semiconductor technology, applied in the direction of semiconductor devices, electrical equipment, transistors, etc., can solve the problems of increasing the cost of conventional 4 f memory cells, increasing the cost of manufacturing, and increasing the cost of additional equipment and processing steps
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Benefits of technology
Problems solved by technology
Method used
Image
Examples
first embodiment
[0048]FIG. 12 shows digit lines 340 added to the layout of FIG. 11. The digit lines 340 are offset from the laterally extending active area arms 165 by about ¼ F in the y direction. The offset of the digit lines 340 enables the digit lines 340, although buried, (see FIG. 13) to avoid the container-style stacked capacitor 335. Bit line contacts 380 couple the digit lines 340 with the active areas 160, as described with respect to the present invention. Word lines 370, depicted in cross-section in FIGS. 14 and 15, may be added to the layout, orthogonally to the digit lines 340, as illustrated in the previous embodiment of the invention of FIG. 7. The word lines 370 couple with the polysilicon gate areas 310 using word line contacts 350 (FIG. 15) positioned over the central region 316 of the polysilicon gate areas 310. Each bit line contact 380 couples four storage nodes 180 of an active area 160 with a digit line 340. Each word line contact 350 couples four neighboring storage nodes 1...
embodiment 41
[0063] A refresh counter 82 stores the address of the row of memory cells to be refreshed either during a conventional auto-refresh mode or self-refresh mode. After the row is refreshed, a refresh controller 84 updates the address in the refresh counter 82, typically by incrementing or decrementing, the contents of the refresh counter 82 by one. Although shown separately, the refresh controller 84 may be part of the control logic circuit 66 in other embodiments of the memory circuit 60. The memory circuit 60 may also include an optional charge pump 86, which steps up the power-supply voltage VDD to a voltage VDDP. In one embodiment 41, the charge pump 86 generates VDDP approximately 1-1.5 V higher than VDD. The memory circuit 60 may also use VDDP to conventionally overdrive selected internal transistors.
[0064]FIG. 17 is a block diagram of an electronic system 1212, such as a computer system, that incorporates the memory circuit 60 of FIG. 16. The system 1212 also includes computer c...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More