Semiconductor device

a technology of semiconductor devices and devices, applied in semiconductor devices, measurement devices, instruments, etc., can solve the problems of increasing the number of probes, reducing the efficiency and cost performance of testing and burn-in, and achieving high-precision burn-in or testing.

Inactive Publication Date: 2007-09-06
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

Enables highly precise wafer level burn-in and simultaneous multiple probe testing without increasing the number of probes, ensuring uniform power supply to all circuit blocks and reducing testing time and costs.

Problems solved by technology

However, when influences of noise interference between a digital circuit and an analog circuit or between a plurality of analog circuits due to sharing of a power supply system and a ground system is not negligible, normally, using some kind of means, power supply systems and ground systems have to be separated.
Therefore, in process steps of fabricating a semiconductor integrated circuit in mass production, how efficiently testing and burn-in can be performed at low cost has become a challenge.
In this testing technique, as the degree of integration is enhanced and the number of chips obtained from a single wafer is increased, its effects in efficiency and cost performance become larger.
However, in this technique, the number of probes becomes a problem.
Especially, in wafer level burn-in, since the number of probes provided per chip is limited because of restrictions for a burn-in equipment, it is not possible to apply probes to all pads of a system LSI at the same time.
Needless to say, this problem more largely influences as the number of chips obtained from a single wafer is increased.
Therefore, the number of pads requiring probes when wafer level burn-in is performed is likely to be increased and thus the number of probes becomes a more serious problem.
However, in each of the first and second known techniques, when wafer level burn-in is performed, a power supply potential is supplied to a plurality of circuit blocks via their respective switch circuits from a single power pad, so that a difference in potential level between power supply potentials of the plurality of circuit blocks is generated.
Therefore, wafer level burn-in is performed in a state where respective potentials applied to the plurality of circuit blocks are different and a stress level becomes non-uniform in a semiconductor integrated circuit.

Method used

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Examples

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first embodiment

[0022]FIG. 1 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. In FIG. 1, a semiconductor integrated circuit 10 includes circuit blocks (blocks A, B and C) 100, 101 and 102. When each of the circuit blocks 100, 101 and 102 is in a normal operation mode, power supply voltages VDDA, VDDB and VDDC are supplied to the circuit blocks 100, 101 and 102 from power supply pads 300, 301 and 302, respectively, through respective power supply lines 200, 201 and 202. In the same manner, ground potentials VSSA, VSSB and VSSC are supplied to the circuit blocks 100, 101 and 102 from ground pads 310, 311 and 312, respectively, through respective ground lines 210, 211 and 212. The semiconductor integrated circuit 10 further includes a test-use power supply pad 303 and a test-use ground pad 313, and the test-use power supply pad 303 and the test-use ground pad 313 supply a power potential WVDD and a ground po...

second embodiment

[0027]FIG. 2 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention. The description of each member also shown in the first embodiment will be omitted.

[0028]Potential transfer circuits 440, 441 and 442 are connected between a test-use power supply line 203 and a power supply line 200, between the test-use power supply line 203 and a power supply line 201 and between the test-use power supply line 203 and a power supply lines 202, respectively. The potential transfer circuits 440, 441 and 442 include as their components switch circuits 503, 504 and 505 each being formed of an NMOS transistor, respectively. In the same manner, potential transfer circuits 450, 451 and 452 are connected between a test-use ground line 213 and a ground line 210, between the test-use ground line 213 and a ground line 211 and between the test-use ground line 213 and a ground line 212, respectively. The potential transfe...

third embodiment

[0033]FIG. 3 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention. Description of each member also shown in the first and second embodiments will be omitted.

[0034]A semiconductor integrated circuit 10 includes a test mode determination pad 351. The test mode determination pad 351 is connected to circuit blocks 100, 101 and 102 through test mode signal lines 250, 251 and 252, respectively. The test mode determination pad 351 is connected to any one of ground lines 210, 211 and 212 via a level shifter 810. The level shifter 810 has a configuration including two resistor devices 530 and 531 connected in series. A potential signal generated according to the resistance ratio between the resistor devices 530 and 531 is connected as a gate signal to each of respective low break-down voltage NMOS switch circuits 516, 517 and 518 of the potential transfer circuits 450, 451 and 452. Respective gates of N...

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Abstract

A power supply potential and a ground potential are supplied to a test-use power supply pad and a test-use ground pad, respectively. The power supply potential supplied to the test-use power supply pad is transferred to power supply lines and then to each circuit block via a test-use power supply line and a potential transfer circuit including a diode device. A voltage drop is caused by each of the diode devices. To cope with the voltage drop, however, respective sizes of the diode devices and resistance components of the potential transfer circuits are configured so that a uniform voltage drop is generated at each of the power supply lines.

Description

BACKGROUND OF THE INVENTION[0001]The present invention relates to techniques for reducing the number of terminals requiring probes when probe testing and wafer level burn-in is performed in fabrication process steps for fabricating a semiconductor device.[0002]In recent years, as the degree of shrinking and integration of semiconductor devices has been enhanced, development of system LSI has become mainstream. In a system LSI, integrated circuits having various different functions are placed within a single chip or a single package, and individual power supply systems and ground systems provided for the integrated circuits, respectively, have to be integrated as a single power supply system and a single ground system of the chip or of the package.[0003]However, when influences of noise interference between a digital circuit and an analog circuit or between a plurality of analog circuits due to sharing of a power supply system and a ground system is not negligible, normally, using so...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G01R31/26
CPCG01R31/2879H01L2224/0603H01L2224/05554H01L24/06H01L2924/14H01L2924/00
InventorOTA, SHUSAKUSEGAWA, HIROAKIHIROFUJI, MASANORI
OwnerSOCIONEXT INC