Enhanced Programming Performance in a Nonvolatile Memory Device Having a Bipolar Programmable Storage Element

Abstract

A nonvolatile memory cell includes a bipolar programmable storage element operative to store a logic state of the memory cell, and a metal-oxide-semiconductor device including first and second source / drains and a gate. A first terminal of the bipolar programmable storage element is adapted for connection to a first bit line. The first source / drain is connected to a second terminal of the bipolar programmable storage element, the second source / drain is adapted for connection to a second bit line, and the gate is adapted for connection to a word line.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) [0001] This application is a continuation of U.S. application Ser. No. 11 / 216,518 filed on Aug. 31, 2005, which claims the benefit of U.S. Provisional Application Ser. No. 60 / 680,563, filed May 13, 2005, the disclosures of which are incorporated by reference herein.FIELD OF THE INVENTION [0002] The present invention relates generally to memory devices, and more particularly relates to enhancing a programming performance of a nonvolatile memory device having a bipolar programmable storage element. BACKGROUND OF THE INVENTION [0003] Bipolar programmable storage elements offer a potential replacement for current non-volatile memory, including, but not limited to, flash memory, one-transistor one-capacitor (1T1C) dynamic random access memory (DRAM) and static random access memory (SRAM). Memory devices employing bipolar programmable storage elements typically rely on a reversal of the polarity of a voltage applied across the storage element in e...

AI Technical Summary

Benefits of technology

The present invention provides a nonvolatile memory device that eliminates the need for an erase operation and reduces complexity of peripheral support circuits. The device includes a bipolar programmable storage element and a metal-oxide-semiconductor device, which allows for efficient memory array layout. The invention also includes a plurality of bit lines and word lines, and a plurality of nonvolatile memory cells operatively coupled to the bit lines and word lines for selectively accessing one or more memory cells in the memory array. The technical effects of the invention include reducing complexity, improving efficiency, and achieving efficient memory array layout.

Problems solved by technology

This intervening erase operation undesirably increases the complexity of circuits that are peripheral to the memory device in order to support the generation of the negative voltages employed, and is therefore an impediment to achieving higher performance in the memory device.

Consequently, the cost of the memory cell, which is directly proportional to memory cell size, would increase accordingly.

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