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Structure of strained silicon on insulator and method of manufacturing the same

a technology of strained silicon and insulator, which is applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of limiting the device yield, implementing the advantages of strained silicon cmos technique, and the thickness of the sige layer is added to the total thickness of the mosfet main body, etc., to achieve small parasitic capacitance and high carrier mobility

Inactive Publication Date: 2007-12-13
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach results in a strained SOI structure with improved device performance, reduced parasitic capacitance, and high carrier mobility, suitable for applications in display panels and next-generation memory and semiconductor devices, without the need for high-temperature annealing processes.

Problems solved by technology

The difficulty in implementing the advantages of the strained silicon CMOS technique is the presence of a relaxed SiGe layer underneath the strained silicon layer.
Therefore, the improvement of device performance and a device yield that can be achieved may be limited during manufacturing a CMOS due to the difficulty of maintaining an integrity of material.
Another disadvantage is that the thickness of the SiGe layer is added to the total thickness of a MOSFET main body.
The addition of a thickness to the MOSFET is especially undesirable to the SOIFET structure since the additional thickness affects adversely to the super slim SOI device in which a MOSFET structure having a very thin channel is included.

Method used

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  • Structure of strained silicon on insulator and method of manufacturing the same
  • Structure of strained silicon on insulator and method of manufacturing the same
  • Structure of strained silicon on insulator and method of manufacturing the same

Examples

Experimental program
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first embodiment

[0033]FIGS. 2A through 2L are cross-sectional views illustrating a method of manufacturing a strained SOI structure according to the present invention. Here, like reference numerals refer to like elements throughout the drawings. The formation of material layers during the processes is formed using a well known thin film deposition apparatus such as ultra high vacuum chemical vapor deposition (UHV-CVD) or low pressure chemical vapor deposition (LPCVD).

[0034] Referring to FIGS. 2A through 2C, a protective layer 12 is formed on a surface of an insulating substrate 10. The protective layer 12 is formed of a material having characteristics of insulating, transparent, and resistance to an echant, such as AlN. Next, a bonding layer 14 formed of a material, such as SiO2 or polycrystalline silicon, is formed on the on the protective layer 12. Here, the protective layer 12 and the bonding layer 14 are not requisite layers.

[0035] Referring to FIGS. 2D through 2H, after preparing a Si substra...

second embodiment

[0040]FIGS. 3A through 3L are cross-sectional views illustrating a method of manufacturing a strained SOI structure according to the present invention. Here, like reference numerals refer to like elements throughout the drawings. The formation of material layers during the processes is formed using a well known thin film deposition apparatus such as UHV-CVD or LPCVD.

[0041] Referring FIGS. 3A through 3C, after preparing an insulating substrate 10, a protective layer 12 is formed on the insulating substrate 10. The protective layer 12 is formed of a material having characteristics of insulating, transparent, and resistance to an echant, such as AlN. A bonding layer 14 formed of SiO2 or polycrystalline silicon is formed on the protective layer 12. The protective layer 12 and the bonding layer 14 are not requisite.

[0042] Referring to FIGS. 3D through 3H, after preparing the Si substrate 20, a SiGe layer 24 having a predetermined thickness is formed on the Si substrate 20. Here, the SiG...

third embodiment

[0047]FIGS. 4A through 4L are cross-sectional views illustrating a method of manufacturing a strained SOI structure according to the present invention. Here, like reference numerals refer to like elements throughout the drawings. The formation of material layers during the processes is formed using a well known thin film deposition apparatus such as UHV-CVD or LPCVD.

[0048] Referring FIGS. 4A through 4C, after preparing the insulating substrate 10, the protective layer 12 is formed on the insulating substrate 10. The protective layer 12 is formed of a material having characteristics of insulating, transparent, and resistance to an echant, such as AlN. The bonding layer 14 formed of SiO2 or polycrystalline silicon is formed on the protective layer 12. The protective layer 12 and the bonding layer 14 are not requisite.

[0049] Referring to FIGS. 4D through 4H, after preparing the Si substrate 20, a SiO2 layer 21 having a predetermined thickness is formed on the Si substrate 20. At least...

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Abstract

Provided is a strained SOI structure and a method of manufacturing the strained SOI structure. The strained SOI structure includes an insulating substrate, a SiO2 layer formed on the insulating substrate, and a strained silicon layer formed on the SiO2 layer.

Description

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS [0001] Priority is claimed to Korean Patent Application No. 10-2004-00103111, filed on Dec. 8, 2004, in the Korean Intellectual Property Office, and as a divisional application of U.S. application Ser. No. 11 / 071,150, filed Mar. 4, 2005, the disclosure of which is incorporated herein in its entirety by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a strained silicon on insulator (strained SOI) structure and a method of manufacturing the same, and more particularly, to a strained SOI structure having a small parasitic capacitance and high carrier mobility and a method of manufacturing the same. [0004] 2. Description of the Related Art [0005] A strained silicon CMOS is a CMOS device that includes a thin, strained silicon layer on a relaxed SiGe layer. The mobility of electrons and holes within the strained silicon layer is known to be much higher than with a bulk silicon lay...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/00
CPCH01L21/32134H01L21/76256H01L21/76259H01L29/7842H01L29/78603H01L27/1266H01L2924/0002Y10S438/933H01L29/78687H01L2924/00H01L21/20H01L21/8238H01L27/12
Inventor PARK, YOUNG-SOOXIANYU, WENXUNOGUCHI, TAKASHI
Owner SAMSUNG ELECTRONICS CO LTD