Methods of forming silicide regions and resulting MOS devices

Abstract

A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source / drain region adjacent the gate dielectric, and a source / drain silicide region on the source / drain region, wherein the source / drain silicide region and the gate silicide region have different metal compositions.

Description

TECHNICAL FIELD[0001]This invention relates generally to the structure and manufacturing methods of metal-oxide-semiconductor (MOS) devices, and more particularly to the formation of silicide regions of MOS devices.BACKGROUND[0002]Deep-submicron scaling required for VLSI systems dominates design considerations in the microelectronics industry. As the gate electrode length is scaled down, the source and drain junctions must be scaled down accordingly to suppress the so-called short channel effects (SCE) that degrade performance of miniaturized devices. A major problem related to complementary metal oxide silicon (CMOS) scaling is the undesirable increase in parasitic resistance. As the source / drain junction depth and polycrystalline silicon line width are scaled into the deep-submicron range, contact resistance becomes more significant and needs to be reduced.[0003]The principle way of reducing contact resistances between polysilicon gates and source / drain regions and interconnect li...

AI Technical Summary

Benefits of technology

[0010]The MOS devices formed using the preferred embodiments of the present invention have improved roll-off resistivities and reliability.

Problems solved by technology

A major problem related to complementary metal oxide silicon (CMOS) scaling is the undesirable increase in parasitic resistance.

The conventional silicidation process, however, suffers drawbacks.

However, it is sensitive to the high temperatures of subsequent processes, such as the formation of highly stressed CESL and / or ILD layers.

Undesired effects such as stringers and encroachments may occur at the source / drain regions in the silicidation process and the effects are pronounced if nickel silicide alone is implemented.

The function and reliability of the integrated circuit is thus adversely affected.

This limits the usage of cobalt silicide in advanced technologies with small scales.

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