Electronic structures utilizing etch resistant boron and phosphorus materials and methods to form same

Abstract

A dense boron-based or phosphorus-based dielectric material is provided. Specifically, the present invention provides a dense boron-based dielectric material comprised of boron and at least one of carbon, nitrogen, and hydrogen or a dense phosphorus-based dielectric comprised of phosphorus and nitrogen. The present invention also provides electronic structures containing the dense boron-based or phosphorus-based dielectric as an etch stop, a dielectric Cu capping material, a CMP stop layer, and/or a reactive ion etching mask in a ULSI back-end-of-the-line (BEOL) interconnect structure. A method of forming the inventive boron-based or phosphorus-based dielectric as well as the electronic structure containing the same are also described in the present invention.

Description

FIELD OF THE INVENTION[0001]The present invention describes dielectric materials comprised of boron or phosphorus in combination with other elements that have high thermal and chemical stability, and methods for fabricating films of these materials and electronic devices containing such films. More particularly, the present invention relates to a dense boron alloy or dense phosphorus alloy dielectric material for use as an etch stop, a cap material, and / or a hard mask / polish stop in an ultra large scale integrated (ULSI) back-end-of-the-line (BEOL) interconnect structure. Electronic structures containing these materials are provided, and methods for fabrication of such films and structures are also described.BACKGROUND OF THE INVENTION[0002]The continuous shrinking in dimensions of electronic devices utilized in ULSI circuits in recent years has resulted in increasing the resistance of the BEOL metallization as well as increasing the capacitance of the intralayer and interlayer diel...

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Benefits of technology

[0014]In one embodiment of the present invention, a BEOL interconnect structure that is robust and tolerant of the problem commonly encountered in BEOL structure fabrication called the “misaligned via” is provided. By “robust” it is meant that during fabrication of the BEOL interconnect structure of the present invention, a via formed on a second metal level may be slightly misaligned with respect to the first metal level below. In a normal prior art structure, when dilute HF cleaning of the via is done, there is damage to

Problems solved by technology

This combined effect increases signal delays in ULSI electronic devices.

A significant problem encountered in forming these BEOL interconnect structures with smaller and smaller dimensions is the etch selectivity is poor between the ILD layer comprised of Si, C, O, and H and the underlying layer.

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