Unlock instant, AI-driven research and patent intelligence for your innovation.

Selective electroplating onto recessed surfaces

Inactive Publication Date: 2008-02-07
EI DU PONT DE NEMOURS & CO
View PDF6 Cites 11 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But to achieve this requires the deposition of a considerable excess of Cu over the entire surface.
Nevertheless, excess Cu deposited in the ECD step generally exceeds the amount of Cu required to fill the circuits.
The need to deposit and then remove a substantial amount of excess Cu is wasteful of time and materials, requires several expensive pieces of equipment, and generates a waste stream contaminated by toxic chemicals.
The consumption of the specialized CMP polishing slurries and pads represents a substantial operating cost.
In addition, the CMP process can be a source of defects and yield loss.
Among the defects associated with Cu CMP are abrasive erosion of the barrier layer and dielectric material on narrow dielectric features.
This problem has become more important with the introduction of low-K dielectric materials, which are mechanically more fragile than SiO2.
Another defect associated with Cu CMP is “dishing”, where over-polishing causes partial loss of Cu in the circuit features such that the surface of these features recedes below the plane of the surrounding dielectric.
If regions of the barrier layer 7 are excessively oxidized or abrasively removed during selective removal of the seed layer, then neighboring recessed areas may become electrically isolated and fail to be plated.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Selective electroplating onto recessed surfaces
  • Selective electroplating onto recessed surfaces
  • Selective electroplating onto recessed surfaces

Examples

Experimental program
Comparison scheme
Effect test

example 1

Over-Polishing of a Cu Damascene Wafer by MMEP

[0061]A Cu damascene test wafer (Sematech 854AZ) was over-polished using MMEP to a point where all excess Cu was removed from plateau areas and the circuit features were dished to the extent than no more than about 200 nm of Cu remained in the recessed areas. (“Over-polishing” is a term of art indicating that the wafer was polished beyond the point where the first area of barrier is exposed.) The electrolyte solution in the cathode half-cell comprised 0.5M CuSO4 in 1.0M aqueous H2SO4. The final stage of polishing employed a Nafion®) N117 membrane embossed with a topographic pattern comprising isolated lands 2.4×104 cm2 separated by continuous channels approximately 50 μm deep. The surface of the wafer was flushed with de-ionized water (˜10 MOhm cm). The interface velocity was held at 10 cm / sec under a hydrostatic pressure of 1.5 psi, while applying 0.1 msec pulses of 6V separated by 0.2 msec intervals producing an interfacial current den...

example 2

Selective Electroplating onto Dished Areas of an Over-Polished Damascene Wafer

[0063]The over-polished test wafer from Example 1 was fitted with a simple electroplating apparatus as illustrated schematically in FIG. 6. A cylindrical Pyrex flange joint 9 with 4 cm rubber O-ring 10 was clamped onto the surface of the wafer at a location approximately 5 cm from the center, creating a cell for exposing a 12.5 cm2 circular area to electroplating solution. Approximately 50 ml of electrolyte solution 11 comprising 18.6 g CuSO4.5H2O, 2.4 g H2SO4 and 0.5 mg of thiourea in 100 ml of water was poured into the cell. A wire 13 extending from the negative terminal of a galvanostat (Model 173, Princeton Applied Research) was clamped onto the surface of the barrier layer 7 at one edge of the wafer located approximately 4 cm from the outer edge of the flange joint. A Cu anode 12 was suspended in the electrolyte solution above the surface of the wafer and connected to the positive terminal of the powe...

example 3

Effect of MMEP Over-Polishing on Electrical Resistance of Exposed Barrier Layer

[0067]Using the MMEP process under conditions similar to Example 2, a Cu damascene test wafer was over-polished to remove all Cu from both plateaus and recessed circuit features so that the entire barrier layer was exposed. The surface of the exposed barrier layer exhibited a bronze colored metallic reflectivity. The sheet resistance was measured to be 20 ohms / square. For comparison, all the Cu was removed from another test wafer of the same initial composition by soaking in a 10% aqueous solution of potassium monopersulfate (Oxone®)). In this case the remaining exposed barrier layer exhibited a silver colored metallic reflectivity and a sheet resistivity of 17 ohms / square.

[0068]These examples show that on direct exposure to MMEP, the Ta barrier layer remains continuous and retains sufficiently low electrical resistance to carry the current densities required for electroplating, for example 0.1 amp / cm2. T...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Metallic bondaaaaaaaaaa
aaaaaaaaaa
Login to View More

Abstract

Processes for electroplating recessed features on a substrate are provided. The processes are useful in applications such as creating Cu interconnects on integrated circuits.

Description

FIELD OF THE INVENTION[0001]This invention is directed to processes for electrochemically depositing metal into recessed features on an otherwise flat substrate without the necessity of concurrently depositing metal on intervening plateau areas. The processes of the invention are useful for creating Cu interconnects on integrated circuits without the need to planarize and remove large amounts of excess Cu.BACKGROUND[0002]Cu interconnects on integrated circuits (IC's) are presently fabricated by a multi-step damascene process. Four stages in this process are illustrated in FIG. 1 and can be summarized briefly as follows. For each layer of interconnects on top of a silicon wafer 1, the circuit pattern is lithographically etched as a series of lines and holes in a dielectric layer 2, for example a layer of SiO2 approximately 500 nm thick. Then, by means of vapor phase deposition, the entire surface is coated with a thin barrier layer 3, for example TaN and Ta approximately 25 nm thick,...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): C25D5/02
CPCC25D5/02C23C28/3455H01L21/32115H01L21/76855H01L21/76873H01L21/76879H05K3/07H05K3/423H05K2201/0338H05K2203/0315H05K2203/0361C23C28/321C23C28/322C23C28/34C23C28/341C23C28/345C25D5/10
Inventor MAZUR, STEPHEN
Owner EI DU PONT DE NEMOURS & CO