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Semiconductor memory device and method of fabricating semiconductor memory device

Inactive Publication Date: 2008-03-13
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there are several problems.
For example, a lithographic limitation causes a physical limitation in the miniaturization in plane.
Therefore, desirable characteristics of the FeRAM cannot be retained.

Method used

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  • Semiconductor memory device and method of fabricating semiconductor memory device
  • Semiconductor memory device and method of fabricating semiconductor memory device
  • Semiconductor memory device and method of fabricating semiconductor memory device

Examples

Experimental program
Comparison scheme
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first embodiment

[0024]First, a semiconductor memory device and a fabricating method of the semiconductor memory device according to a first embodiment of the present invention will be described below in detail with reference to the drawing mentioned above.

[0025]FIG. 1 is a schematic cross-sectional view showing a ferroelectric memory including a memory cell portion in a first embodiment of the present invention. FIG. 2 is a schematic plane view along line A-A in FIG. 1 showing the ferroelectric memory including the memory cell portion in the first embodiment of the present invention. FIG. 3 is an equivalent circuit diagram showing the ferroelectric memory including the memory cell portion in the first embodiment of the present invention.

[0026]The ferroelectric capacitor and the memory cell are formed over a semiconductor substrate in layer in the first embodiment.

[0027]As shown in FIG. 1, a ferroelectric memory 40 is a Chain FeRAM (Ferroelectric Random Access Memory) as a ferroelectric memory. The ...

second embodiment

[0063]Next, a semiconductor memory device and the fabricating method of the semiconductor memory device according to a second embodiment of the present invention will be described below in detail with reference to the drawing mentioned above. FIG. 10 is a schematic cross-sectional view showing a ferroelectric memory including a memory cell portion in the second embodiment of the present invention. In the second embodiment, a substrate formation method of a memory cell transistor in a Chain FeRAM as a ferroelectric memory is changed as compared with the substrate formation method in the first embodiment.

[0064]It is be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified.

[0065]As shown in FIG. 10, a ferroelectric memory 40a is a Chain FeRAM as a ferroelectric memory. The ferroelectricmemory 40a having a plurality of cyl...

third embodiment

[0085]Next, a semiconductor memory device according to a third embodiment of the present invention will be described below in detail with reference to the drawing mentioned above. FIG. 14 is a schematic plane view showing a ferroelectric memory including a memory cell portion in the third embodiment of the present invention. In this embodiment, a feature of a memory cell portion in a Chain FeRAM as a ferroelectric memory is changed as compared with the feature of the memory cell portion in the first embodiment.

[0086]It is be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified.

[0087]As shown in FIG. 14, a memory cell portion of a ferroelectric memory 40b has a square prism type. The center of the memory cell portion with the square prism type is a capacitor region Ecap composed of the ferroelectric film 5. A periphera...

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PUM

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Abstract

According to an aspect of the present invention, there is provided a semiconductor memory device, comprising a memory cell portion, the memory cell portion having a ferroelectric capacitor and a memory cell transistor, the ferroelectric capacitor having a plurality of electrode films and a ferroelectric film, the plurality of electrode films being stacked in layer on a semiconductor substrate, the ferroelectric film being formed between the plurality of electrode films, a source and a drain of the memory cell transistor being formed between the electrode films, the source and the drain directly contacting the ferroelectric film or indirectly contacting the ferroelectric film via an insulator, one of the source and the drain being connected to one end of the electrode film, the other of the source and the drain being connected to the other end of the electrode film.

Description

CROSS REFERENCE TO RELATED APPLICATION[0001]This application is based upon and claims the benefit of priority from the prior Japanese Application (No. 2006-244760, filed Sep. 8, 2006), the entire contents of which are incorporated herein by reference.FIELD OF THE INVENTION[0002]The present invention relates to a semiconductor memory device and a method of fabricating the semiconductor memory device, and in particular, to a ferroelectric memory device and a method of fabricating the ferroelectric memory device.DESCRIPTION OF THE BACKGROUND[0003]A non-volatile memory in next generation have been developed to realize that rewriting speed and number of rewriting of the non-volatile memory are higher than and five orders of magnitude larger than those of a conventional EEPROM or a conventional flash memory, respectively. Furthermore, it is desirable that characteristics of the non-volatile memory such as capacity, speed or cost are comparable with those of a conventional DRAM.[0004]A FeR...

Claims

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Application Information

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IPC IPC(8): H01L27/108H01L21/8242
CPCH01L27/0688H01L27/11507H01L27/11502H10B53/30H10B53/00
Inventor HIDAKA, OSAMU
Owner KK TOSHIBA
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