Hardmask for improved reliability of silicon based dielectrics

Abstract

The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

Description

RELATED APPLICATION [0001] This application is a continuation of U.S. patent application Ser. No. 10 / 981,233, filed Nov. 4, 2004.FIELD OF THE INVENTION [0002] The present invention generally relates to integrated circuits (ICs), and more particularly to silicon based dielectrics using interconnect structures, including multilevel interconnect structures fabricated by damascene methods, in which the dielectric is a low k dielectric having a dielectric constant of about 3.0 or less. The present invention describes improved reliability of silicon based dielectrics as well as interconnect structures containing metal wiring such as copper within these low k dielectrics, the structures are improved by introducing a dense, graded hardmask on top of each of the silicon based dielectrics. The present invention also describes a method to make the inventive hardmask structure as well as a method to use in the inventive hardmask in an interconnect structure. BACKGROUND OF THE INVENTION [0003] G...

AI Technical Summary

Benefits of technology

[0009] The present invention provides a back-end-of-the-line (BEOL) interconnect structure of either the dual or single damascene type in a low k dielectric (k of about 3.0 or less, preferably less than about 2.8, and more preferably less than about 2.5) with improved reliability. The inventive BEOL interconnect structures formed in the low k dielectric are very stable and have reliable electrical characteristics, such as leakage, metal resistance and capacitance, during field operation or reliability stress as compared with conventional BEOL interconnect structures formed in low k dielectrics. Additionally, the inventive BEOL interconnect structure does not exhibit delamination or moisture adsorption that eventually would lead to poor dielectric breakdown.

Problems solved by technology

However, reliability problems are associated with these prior art structures.

During integration, reliability stress, or extended use, a chip interconnect structure made in a low k dielectric may fail or degrade due to poor adhesion, moisture uptake, and various stress migration between the metal liner / metal and the low k dielectric.

This poor quality and reliability results from the defects in the low k dielectric film and the metal liner, allowing metal or metal ions, e.g., Cu or Cu ions, to penetrate the dielectric allowing oxidizing species such as H2O or O2 to interact with the metal, The problems become serve with the introduction of porous low k films where nanopores are present in the film to reduce the dielectric constant of the same.

The mechanical properties of these porous low k films are less robust as compared to a conventional SiO2 dielectric for subsequent device fabrication and packaging.

As a result, significant interlevel dielectric film cracking may occur as the low k dielectric film becomes more porous, especially when it is exposed to moisture.

Moreover, the effective cohesive strength of porous low k films is reduced, as the dielectric film is prone to stress cracking.

In an integrated structure and when a blanket dielectric layer is deposited over an underlying patterned layer, the driving force for cracking increases due to the thermal mismatch between the metal interconnect lines and the dielectric.

As a result, cracking may occur in the overlying blanket dielectric film even though the film itself does not contain enough driving force to induce cracking.

In view of the above, there is a need to prevent moisture absorption, reduce cracking and improve mechanical properties of low k dielectric films and to enhance the reliability of the metal / low k dielectric interconnect faces by reducing the defect of the low k dielectrics that are caused by open pores and result in easy moisture adsorption during subsequent processing steps, poor adhesion between interfaces, increased cracking force and ultimately failed device reliability.

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