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Metal-Insulator-Metal Capacitor

a technology of metal-insulator and capacitor, which is applied in the direction of capacitor, semiconductor device details, semiconductor/solid-state device details, etc., can solve the problems of high cost and the number of steps, the known method of fabricating a mim capacitor is limited, and the capacitor resistance changes, so as to reduce exposure, development and etching treatment, the effect of simplifying the fabrication of the capacitor

Inactive Publication Date: 2009-11-05
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach simplifies the fabrication process, reduces costs, and avoids excessive or insufficient etching, resulting in a more reliable and cost-effective MIM capacitor with improved linearity.

Problems solved by technology

Polysilicon electrodes would bring about a problem of insufficient carriers, which leads to the capacitance changes with the surface voltage across both ends of the capacitor.
The known method for fabricating a MIM capacitor is limited by its high cost and the number of steps, since the formation of upper electrode and lower electrode should be carried out respectively and the exposure, development and etching treatment are repeated.
Moreover, due to the fact that the formation of contact holes on the upper electrode and the lower electrode is carried out simultaneously, but there is a difference in the height between the upper electrode and the lower electrode, it has the risk of an excessive etching to the contact hole connecting with the upper electrode and an insufficient etching to the contact hole connecting with the lower electrode.

Method used

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  • Metal-Insulator-Metal Capacitor
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  • Metal-Insulator-Metal Capacitor

Examples

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first embodiment

[0030]FIG. 7 is a flow diagram illustrating a method for fabricating metal-insulator-metal capacitor according to the present invention. As shown in FIG. 7, an interlayer dielectric layer is formed on a semiconductor substrate by carrying out the step S201.

[0031]In this embodiment, the interlayer dielectric layer is made of silicon oxide or Borophosphosilicate Glass (BPSG) and the manner of forming the interlayer dielectric layer is the well-known chemical vapor deposition.

[0032]An insulation trench is formed in the interlayer dielectric layer to run through the interlayer dielectric layer and allow semiconductor substrate to be exposed by carrying out the step S202.

[0033]In this embodiment, the insulation trench is formed by dry etching the interlayer dielectric layer until the semiconductor substrate is exposed.

[0034]The insulation trench is filled with insulation material to form an insulation structure by carrying out the step S203.

[0035]In this embodiment, the insulation materi...

second embodiment

[0040]FIG. 8 is a flow diagram illustrating a method for fabricating metal-insulator-metal capacitor according to the present invention. As shown in FIG. 8, an interlayer dielectric layer is formed on a semiconductor substrate by carrying out the step S301.

[0041]In this embodiment, the interlayer dielectric layer is made of silicon oxide or Borophosphosilicate Glass (BPSG) and the manner of forming the interlayer dielectric layer is the well-known chemical vapor deposition.

[0042]Two metal trenches are formed in the interlayer dielectric layer to run through the interlayer dielectric layer and allow the semiconductor substrate to be exposed by carrying out the step S302.

[0043]In this embodiment, the metal trenches are formed by dry etching the interlayer dielectric layer until the semiconductor substrate is exposed.

[0044]The metal trenches are filled with metal material to form the electrodes of the capacitor by carrying out the step S303.

[0045]In this embodiment, the metal material ...

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Abstract

The present invention provides a metal-insulator-metal capacitor, which comprises a semiconductor substrate; an interlayer dielectric layer disposed on the semiconductor substrate; and an insulation trench and two metal trenches all running through the interlayer dielectric layer and allowing the semiconductor substrate to be exposed; wherein the metal trenches being located on each side of the insulation trench and sharing a trench wall with the insulation trench respectively, the insulation trench being filled with insulation material as an insulation structure, the metal trenches being filled with metal material as electrodes of the capacitor.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS[0001]This application is a divisional of prior application Ser. No. 11 / 833,236, filed Aug. 3, 2007, the entire disclosure of which is hereby incorporated by reference.FIELD OF THE INVENTION[0002]The present invention relates to a semiconductor device and a fabrication method thereof, and more particularly to a metal-insulator-metal capacitor and a fabrication method thereof.DESCRIPTION OF THE RELATED ART[0003]In a very large scale integrated circuit, a capacitor is one type of commonly used passive elements. The capacitor is usually integrated into an active element such as a bipolar transistor or a Complementary Metal Oxide Semiconductor (CMOS) transistor. The current techniques for fabricating a capacitor can be classified into two groups, one employs polysilicon as electrodes and the other employs metal as electrodes. Polysilicon electrodes would bring about a problem of insufficient carriers, which leads to the capacitance changes with th...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01G4/00H10B12/00
CPCH01L28/55H01L23/5223H01L2924/0002H01L2924/00
Inventor WANG, YUANZHANG, BUXIN
Owner SEMICON MFG INT (SHANGHAI) CORP