Method and apparatus for chemical mechanical polishing of large size wafer with capability of polishing individual die

Abstract

A novel polisher for chemical mechanical planarization process is described. The polisher design can have many variations. For process development and consumable evaluation, the CMP process can be performed on a single die or a section of the wafer. The size of testing wafer can be as small as 2″ and as large as 18″. Furthermore, several variations can characterize the slurry for their static etch rate, dynamic etch rate, material removal rate, and viscosity in a single experiment. For production level wafer processing, Chemical Mechanical Polishing of all dies on the wafer surface is achieved by using multi-armed polishing heads or a single polishing head with small piece of a pad at the bottom of the head. The within wafer uniformity can be easily controlled and the equipment can be easily scaled up or down. This inventive design may translate to significant cost reduction for wafer processing at production level as well as evaluation of consumables at research and development level.

Description

INCORPORATION BY REFERENCE[0001]Any foregoing applications and all documents cited therein or during their prosecution (“application cited documents”) and all documents cited or referenced in the application cited documents, and all documents cited or referenced herein (“herein cited documents”), and all documents cited or referenced in herein cited documents, together with any manufacturer's instructions, descriptions, product specifications, and product sheets for any products mentioned herein or in any document incorporated by reference herein, are hereby incorporated herein by reference, and may be employed in the practice of the invention.FIELD OF THE INVENTION[0002]This invention relates to a method of chemical mechanical polishing (CMP) for microelectronics applications. Specifically, the invention is directed to an apparatus of chemical mechanical polishing used for large size patterned / blanket wafer polishing, a process allowing polishing an individual die at a time, and a ...

AI Technical Summary

Benefits of technology

[0009]The third aspect of the present invention is an effective and efficient method to achieve planarization on the selected area on the wafer surface or the entire wafer.

Problems solved by technology

Furthermore, on the 2″ wafers produced by this method only one die is usable.

Another motivation for adapting this approach is the ever increasing cost and complexity of a full wafer or production polisher.

It is widely recognized that, with the ever increase in wafer size, a number of scale up issues are becoming more and more apparent.

Significant effort has been spent and complicated schemes must be in place to maintain the within-wafer-non-uniformity for wafers larger than 200 mm.

It is increasingly difficult to optimize planarity at global level without severe over polishing at some local levels.

Furthermore, a compromise of such at lower level poses greater threat on defectivity at higher level.

In other words, with the significant increase in wafer size and challenges to maintain within wafer uniformity and defectivity, the conventional design is no longer a best choice.

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