Semiconductor device

Abstract

The semiconductor device includes: a semiconductor chip; a die pad for holding the semiconductor chip; a lead; and a sealing resin material for sealing the semiconductor chip, the die pad and an inner portion of the lead. The die pad has an upset portion protruding upward to form a flat face smaller in area than the semiconductor chip, and the portion of the die pad excluding the upset portion is covered with a buffer resin material smaller in elasticity than the sealing resin material.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority under 35 U.S.C. §119 on Patent Application No. 2008-278088 filed in Japan on Oct. 29, 2008 and Patent Application No. 2009-73699 filed in Japan on Mar. 25, 2009, the entire contents of which are hereby incorporated by reference.BACKGROUND OF THE INVENTION[0002]The present invention relates to a semiconductor device including at least one semiconductor chip sealed in a package.[0003]At present, a standardized surface-mount type semiconductor package is configured as follows: a semiconductor chip is fixed to a die pad of a lead frame made of a cupper (Cu) alloy or an iron-nickel (Fe—Ni) alloy by die bonding, a bonding pad (electrode pad) of the semiconductor chip and the end of each lead of the lead frame are wire-bonded to each other with a metal wire made of gold (Au) and the like, and the resultant chip is resin-molded using a mold having a predetermined shape.[0004]In recent years, with the progression o...

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Benefits of technology

[0030]The above configuration improves the heat dissipation of the buffer resin material.

[0031]As described above, in a chip-stacked semiconductor device in which semiconductor chips are stacked one on another on a metal plate (die pad) high in heat conductivity for obtaining high heat dissipation performance, there is a high risk, caused by the difference in the coefficient of linear expansion depending the component materials and heat, that the semiconductor chips and the metal plate may warp and the sealing resin material may peel off from these components due to failure in balancing of the internal stress.

[0032]According to the present invention, the region of the metal plate, which also serves as the heat dissipation plate, excluding the contact portion thereof with the semiconductor chip is coated with a low-elastic resin material as a buffer, or otherwise a cross-sectional structure high in anchor effect is adopted for the metal plate, and yet an area large enough to ensure heat conduction is guaranteed.

[0033]Specifically, a step portion is provided in the center of the metal plate, to have a flat face smaller in area than the chip size. With this, warping due to the stress with chip attachment in the fabrication process can be reduced, and the flatness of the top face of the semic

Problems solved by technology

The conventional multi-chip semiconductor device described above, which includes a plurality of semiconductor chips stacked one upon another, is large in the number of signal buses and power consumption.

However, since the coefficient of linear expansion is greatly differen

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