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Semiconductor device

Inactive Publication Date: 2010-04-29
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0009]To overcome the problem described above, an object of the present invention is to provide a semiconductor device packaged with a sealing resin material in which the thermal stress between component materials is dispersed and warping of semiconductor chips is suppressed to enhance the flatness between the chips, to thereby improve the reliability.
[0034]As described above, according to the semiconductor device of the present invention, packaged with a sealing resin material, the thermal stress between component materials is dispersed and warping of semiconductor chips is suppressed. As a result, the flatness between the chips improves, and hence the reliability can be greatly improved.

Problems solved by technology

The conventional multi-chip semiconductor device described above, which includes a plurality of semiconductor chips stacked one upon another, is large in the number of signal buses and power consumption.
However, since the coefficient of linear expansion is greatly different between the metal plate and a resin material, the chip may have warping and internal stress that may impede the layered structure high in the flatness between a plurality of semiconductor chips, causing a problem that the reliability of the semiconductor device decreases.

Method used

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  • Semiconductor device
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Examples

Experimental program
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Effect test

embodiment 1

Fifth Alteration of Embodiment 1

[0069]FIG. 4 shows a partial cross-sectional configuration of the peripheral portion of the die pad 2 and the buffer resin material 8 covering the peripheral portion.

[0070]In the fifth alteration, grains 9 made of an inorganic material or a metal high in thermal conductivity are added to or mixed in the buffer resin material 8. For the grains 9, silica, alumina, titania, aluminum, copper, silver or the like may be used. The added amount of the grains 9 to the buffer resin material 8 may be roughly in the range of 20% to 60%. Having such grains, the heat dissipation capability of the buffer resin material improves, and thus the reliability of the semiconductor device can be enhanced.

[0071]The fifth alternation is applicable to any of Embodiment 1 and the first to fourth alterations.

Embodiment 2

[0072]Example Embodiment 2 will be described with reference to the relevant drawings.

[0073]FIG. 5 diagrammatically shows a cross-sectional configuration of a ch...

embodiment 2

Alteration of Embodiment 2

[0086]FIG. 7A shows a plan configuration of the die pad 2 having the upset portion 2a and the down-set portion 2b in an alteration of example Embodiment 2, and FIG. 3B shows a cross-sectional configuration taken along line VIIb-VIIb in FIG. 7A.

[0087]In general, when the sealing resin material 7 and the first and second semiconductor chips 3A and 3B are relatively thick, the thicknesses of the first and second semiconductor chips 3A and 3B and the sealing resin material 7 are dominant for the rigidity of the semiconductor device itself. In this case, warping does not occur with the stress at the contact portion between the top face of the upset portion 2a as the inner portion of the die pad 2 and the first semiconductor chip 3A attached together via the adhesive paste 4, which tends to expand or contract during temperature cycling testing and reflowing. Instead, interface fracture may occur with high probability.

[0088]In this alteration, therefore, the shape...

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Abstract

The semiconductor device includes: a semiconductor chip; a die pad for holding the semiconductor chip; a lead; and a sealing resin material for sealing the semiconductor chip, the die pad and an inner portion of the lead. The die pad has an upset portion protruding upward to form a flat face smaller in area than the semiconductor chip, and the portion of the die pad excluding the upset portion is covered with a buffer resin material smaller in elasticity than the sealing resin material.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority under 35 U.S.C. §119 on Patent Application No. 2008-278088 filed in Japan on Oct. 29, 2008 and Patent Application No. 2009-73699 filed in Japan on Mar. 25, 2009, the entire contents of which are hereby incorporated by reference.BACKGROUND OF THE INVENTION[0002]The present invention relates to a semiconductor device including at least one semiconductor chip sealed in a package.[0003]At present, a standardized surface-mount type semiconductor package is configured as follows: a semiconductor chip is fixed to a die pad of a lead frame made of a cupper (Cu) alloy or an iron-nickel (Fe—Ni) alloy by die bonding, a bonding pad (electrode pad) of the semiconductor chip and the end of each lead of the lead frame are wire-bonded to each other with a metal wire made of gold (Au) and the like, and the resultant chip is resin-molded using a mold having a predetermined shape.[0004]In recent years, with the progression o...

Claims

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Application Information

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IPC IPC(8): H01L23/485
CPCH01L23/4334H01L23/49503H01L23/49575H01L2224/32014H01L2224/32145H01L24/48H01L2224/48247H01L2224/73265H01L2924/01079H01L2924/3511H01L2224/32245H01L2224/48095H01L2924/00014H01L2924/00012H01L2924/00H01L2224/451H01L2224/45144H01L2924/181H01L24/73H01L2224/32055H01L24/45H01L2924/00015H01L2224/05599H01L2224/45015H01L2924/207
Inventor SATOU, MOTOAKI
Owner PANASONIC CORP
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