Polishing pad

Abstract

A polishing pad which comprises a laminate of an abrasive layer with a cushioning layer. The abrasive layer has a Microrubber A hardness of 75 degrees or higher and a thickness of 0.8-3.0 mm. The cushioning layer comprises an unfoamed elastomer and has a thickness of 0.05-1.5 mm. The abrasive layer has at least two kinds of grooves formed in the surface. One of the two kinds of grooves is first grooves and the other is second grooves. The first grooves each has a groove width of 0.5-1.2 mm, and has a groove pitch of 7.5-50 mm. The second grooves each has a groove width of 1.5-3 mm, and has a groove pitch of 20-50 mm. Each of the first grooves and each of the second grooves are open to side edge faces of the abrasive layer.

Description

FIELD OF THE INVENTION[0001]The invention relates to a polishing pad. The polishing pad is to be used as a preferable polishing means in the following polishing steps: a polishing step to planarize a surface of a semiconductor substrate and a polishing step to planarize a surface of an insulation layer or a surface of metal wiring formed on a semiconductor substrate.BACKGROUND OF THE INVENTION[0002]Circuits with increasingly higher density have been developed every year for large scale integrated circuits (LSI) such as for semiconductor memory devices. Products with higher density require semiconductor devices of increased degrees of lamination. As the degree of lamination increases, more serious problems have been taking place in association with the irregularities caused by the lamination in the principal plane of the semiconductor substrate. Thus, studies on semiconductor substrate planarization processes using Chemical Mechanical Polishing (CMP) technique have been performed wit...

AI Technical Summary

Benefits of technology

[0010]The invention aims to provide a polishing pad that has a high polishing stability and planarizing capability when used in planarization processes such as for planarizing a semiconductor substrate and for polishing a surface of an insulation layer or a surface of metal wiring formed on a semiconductor substrate, and that has only a small pad-to-pad variation in polishing performance.

[0028]The invention provides a polishing pad having a high polishing stability and planarizing capability, together with a limited pad-to-pad variation in polishing performance.

Problems solved by technology

On conventional two layer polishing pads, laminated pads composed of a cushioning layer of foamed material having a relatively low compression modulus such as polyurethane impregnated nonwoven fabric or soft foamed polyurethane generally have defects such as insufficient planarizing capability and tendency of the planarizing capability deteriorating with a decreasing thickness of an abrasive layer caused by the polishing.

On conventional two layer polishing pads, furthermore, laminated pads composed of a cushioning layer of unfoamed elastomer having a high compression modulus or foamed material having a high density generally have defects such as difficulty in achieving stable polishing by using grooves of conventional shapes provided in an abrasive layer and a large pad-to-pad variation in polishing performance.

Thus, the conventional polishing pads have problems such as insufficient polishing stability, low planarizing capability, and large pad-to-pad variation in polishing performance.