Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor

Abstract

A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device.

Description

FIELD OF THE INVENTION[0001]The present invention relates to a method of converting commercial microprocessors to radiation-hardened processors and, more particularly, to a method to modify a commercial microprocessor for radiation-hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation-hardened applications, and the resulting microprocessor.BACKGROUND[0002]Currently available microprocessors designed for space and military applications do not meet the performance and functional requirement integrated circuits of many proposed new systems. For example, the current offerings from manufacturers of military and space components are limited to technologies circa 150 nm and above. These offerings are limited by the intrinsic capabilities of the semiconductor facilities being used, with investment to get those fabs to state-of-the-art manufacturing being in the hundreds of millions of dollars ...

AI Technical Summary

Benefits of technology

[0010]In yet another aspect of the invention, a method comprises: obtaining an existing microprocessor design; targeting a low-power SOI process; performing a physical-design (PD) step with robust power distribution to provide immunity to neutron bursts; and at least one of: providing immunity to SEUs in logic portions of the microprocessor design; and providing immunity to SEUs in memory portions of the microprocessor design.

Problems solved by technology

Currently available microprocessors designed for space and military applications do not meet the performance and functional requirement integrated circuits of many proposed new systems.

For example, the current offerings from manufacturers of military and space components are limited to technologies circa 150 nm and above.

These offerings are limited by the intrinsic capabilities of the semiconductor facilities being used, with investment to get those fabs to state-of-the-art manufacturing being in the hundreds of millions of dollars and the operating costs and sustaining engineering costs making the investment unaffordable even for the government.

However, commercially available microprocessors meet the performance and function requirements of such space and military applications, but are not radiation hardened sufficiently for these applications.

For example, commercial integrated circuits have higher performance, function, and density compared with integrated circuits designed for space and military applications; however, designs for such commercial integrated circuits result in failure caused by Single Event Upsets (SEUs) in space applications.

For example, ionizing radiation in space (and ground) based applications directly upsets storage circuits, such as DRAMs, SRAMs, register files and flip-flops.

Moreover, radiation events in combinational logic create voltage glitches that can be latched.

Also, SEUs may cause the circuit to perform incorrect or illegal operations; whereas, an accumulation of radiation over a long period of time may additionally lead to complete device failure.

The high-energy cosmic protons and ions are known to produce secondary fragments which cause SEUs and single event latchups (SELs), as well as total failure resulting from total dose (long accumulation of radiation) in semiconductor ICs.

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