Via structure in multi-layer substrate and manufacturing method thereof

Abstract

Disclosed is a via structure in a multi-layer substrate, comprising a first metal layer, a dielectric layer and a second metal layer. The first metal layer has an upper surface. The dielectric layer covers the first metal layer in which a via is opened to expose the upper surface. The second metal layer is formed in the via and contacts an upper surface and an inclined wall of the via. A contacting surface of the second metal layer has a top line lower than the upper edge of the inclined wall. Alternatively, the second metal layer can be formed on the dielectric layer as being a metal line simultaneously as formed in the via as being a pad. The metal line and the pad are connected electronically. The aforesaid metal second layer can be formed in the via and on the dielectric layer by a metal lift-off process.

Description

CROSS REFERENCE TO RELATED APPLICATION[0001]This is a division of a U.S. patent application Ser. No. 12 / 582,647, filed on Oct. 20, 2009, the disclosure of which is incorporated by reference herein.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention generally relates to a via structure in a multi-layer substrate and the manufacturing method thereof, and more particularly to a via structure in a flexible multi-layer substrate and the manufacturing method thereof.[0004]2. Description of Prior Art[0005]Miniaturization of all electronic products is an inevitable trend in this modern world. While the scales of the semiconductor chips continuously get smaller, the scale of the related technology for packaging needs to be microminiaturized to follow the scale of the semiconductor chip is also inevitably getting smaller. Today, because the routing density of integrated circuits has been greatly increased, using a multi-layer substrate as being a package subs...

AI Technical Summary

Benefits of technology

The present invention provides a via structure in a multi-layer substrate and manufacturing method that can be used in the field of manufacturing package substrates, print circuit boards, flexible package substrates, and flexible print circuit boards. The via structure has a smaller via land than previous designs, which increases the routing density of the substrates and print circuit boards. The via structure also promotes reliability in frequently bended areas of flexible package substrates and print circuit boards. The manufacturing method involves steps of forming metal layers, covering them with a dielectric layer, opening a via, coating a photoresist layer, and removing the photoresist layer. The technical effects of the invention include increased routing density and reliability in flexible package substrates and print circuit boards.

Problems solved by technology

While the scales of the semiconductor chips continuously get smaller, the scale of the related technology for packaging needs to be microminiaturized to follow the scale of the semiconductor chip is also inevitably getting smaller.

Meanwhile, the via land size A of such via structure has to be larger than the via diameter B. In consequence of limitation about the via pitches and metal line pitches of the multi-layer substrate, application to the high integration products will be failed.

Therefore, the via land size A of such kind of via structure has to be larger than the via diameter B. Still, in consequence of limitation about the via pitches and metal line pitches of the multi-layer substrate, further application to the higher routing density today cannot be realized.

Accordingly, the via land size cannot be further minified because the design tolerance of the etching process has to be considered.

As finer the metal lines and sizes of the via structures are required, the etching method has limitation and cannot satisfy coming demands of the multi-layer substrate products.

Similar drawback appears, if the semi-additive process method is employed to manufacture the via structures of the multi-layer substrate, the photoresist layer 410 cannot determine the via land 400 size exactly.

Because the design tolerance of the semi-additive process has to be further considered and via land size accordingly cannot be minified.

As finer the metal lines and sizes of the via structures are required strictly, the semi-additive method also has limitation and cannot satisfy coming demands of the multi-layer substrate products today and in the near future.

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