Ultra low power memory cell with a supply feedback loop configured for minimal leakage operation

Abstract

A memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch having two storage nodes Q and QB, and a supply node. A gating device couples the supply node of the latch to the supply voltage. The gating device is controlled by a feedback loop coming from storage node QB. Due to the aforementioned asymmetric topology, the writing of logic “1” and the writing of logic “0” are carried out differently. Contrary to standard SRAM cells, in the hold states, only the QB storage node presents a valid value of stored data. The feedback loop cuts off the supply voltage for the latch such that the latch is no longer an inverting latch. By cutting off the supply voltage at the stable hold states, while maintaining readability of the memory cell, leakage currents associated with the hold states are eliminated altogether.

Description

BACKGROUND

[0001] 1. Technical Field

[0002] Embodiments of the present invention relate to semiconductor memory devices, and more particularly to an ultra low power consumption random access memory cell that is designed for minimal leakage operation.

[0003] 2. Discussion of the Related Art

[0004] The ongoing demand for ultra low power consumption integrated circuits lead to sub-threshold and near-threshold operation of digital circuits. These approaches utilize very low supply voltages for digital circuit operation, decreasing the dynamic power quadratically, and sufficiently reducing leakage currents. As static power is often the primary factor in a system's power consumption, especially for low to medium performance systems, supply voltage scaling for minimization of leakage currents is essential. Optimal power-delay studies show that the Minimum Energy Point (MEP) is found in the sub-threshold region, where ultra-low power figures are achieved, at the expense of orders-of-magnitude loss ...

Images