Ultra low power memory cell with a supply feedback loop configured for minimal leakage operation

Abstract

A memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch having two storage nodes Q and QB, and a supply node. A gating device couples the supply node of the latch to the supply voltage. The gating device is controlled by a feedback loop coming from storage node QB. Due to the aforementioned asymmetric topology, the writing of logic “1” and the writing of logic “0” are carried out differently. Contrary to standard SRAM cells, in the hold states, only the QB storage node presents a valid value of stored data. The feedback loop cuts off the supply voltage for the latch such that the latch is no longer an inverting latch. By cutting off the supply voltage at the stable hold states, while maintaining readability of the memory cell, leakage currents associated with the hold states are eliminated altogether.

Description

BACKGROUND[0001]1. Technical Field[0002]Embodiments of the present invention relate to semiconductor memory devices, and more particularly to an ultra low power consumption random access memory cell that is designed for minimal leakage operation.[0003]2. Discussion of the Related Art[0004]The ongoing demand for ultra low power consumption integrated circuits lead to sub-threshold and near-threshold operation of digital circuits. These approaches utilize very low supply voltages for digital circuit operation, decreasing the dynamic power quadratically, and sufficiently reducing leakage currents. As static power is often the primary factor in a system's power consumption, especially for low to medium performance systems, supply voltage scaling for minimization of leakage currents is essential. Optimal power-delay studies show that the Minimum Energy Point (MEP) is found in the sub-threshold region, where ultra-low power figures are achieved, at the expense of orders-of-magnitude loss ...

AI Technical Summary

Benefits of technology

[0008]One aspect of the present invention provides a memory cell with an internal supply feedback loop which significantly reduces leakage currents flowing through the latch, compared with standard eight-transistor static SRAM cell 200. The memory cell includes: a latch having a supply node, a ground node, a storage node Q, and a storage node QB; a gating device having a control node and further connected to a voltage supply and to the supply node of the latch; and a feedback loop connecting storage node QB with the control node of the gating device, wherein the ground node of the latch is connected to ground and wherein storage node Q and the storage node QB are connected each to a different write circuitry. Due to the aforementioned asymmetric topology, the writing of logic “1” and the writing of logic “0” into the memory cell are carried out differently. In contrary to a standard SRAM cell, in the hold states, only the QB storage node presents a valid value of stored data. This is because at steady state, both after writing logic “0” and after writing logic “1”, the feedback loop cuts off the supply voltage for the latch such that the latch is no longer an inverting latch (but it is stable all the same). By cutting off the supply voltage at the stable hold states, while maintaining readability of the memory cell, leakage currents associated with the hold states characterizing the operation of static memory cells are eliminated altogether in the memory cell provided herein.

Problems solved by technology

Optimal power-delay studies show that the Minimum Energy Point (MEP) is found in the sub-threshold region, where ultra-low power figures are achieved, at the expense of orders-of-magnitude loss in performance.

However, when ratioed designs are put under extreme conditions, maintaining functionality becomes challenging.

Local mismatch brings an even tougher challenge, as the drive strength ratios between similar devices can be affected, and symmetrically designed circuits can easily lose functionality.

Even if functionality is achieved at all process corners, local mismatch can cause failure.

However, accessing the data stored in the cell is a ratioed process, including a contention between a pull up and a pull down network in both read and write operations.

However, at low voltages, process variations and mismatch cause a loss of functionality.

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