Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Transistor structure and related transistor packaging method thereof

a technology of transistors and transistors, applied in the direction of semiconductor devices, electrical devices, semiconductor/solid-state device details, etc., can solve the problems of high energy loss, damage to semiconductor elements, poor efficiency and high spike voltage value, etc., and achieve the effect of improving efficiency

Inactive Publication Date: 2013-03-14
SPI ELECTRONICS
View PDF60 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a transistor structure and a related packaging method for a snubber circuit that can protect components efficiently and improve efficiency. The transistor structure can simplify the process, reduce size, and increase the withstanding voltage. A two-pin transistor structure is designed to connect an active component or a load in parallel to absorb spikes or noise generated by the active component while the active component is switching at a high frequency. The packaging of the transistor structure can simplify the process, reduce size, increase the withstanding voltage, and improve the efficiency and reduce the spike voltage of the power supply of the snubber circuit.

Problems solved by technology

However, the RCD snubber circuit has disadvantages like the high energy loss, poor efficiency and high spike voltage value, so the use of conventional RCD snubber circuit could easily lead to the damage of the semiconductor elements.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Transistor structure and related transistor packaging method thereof
  • Transistor structure and related transistor packaging method thereof
  • Transistor structure and related transistor packaging method thereof

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0054]Please refer to FIG. 1A, which is a diagram illustrating a transistor structure according to the present invention. The transistor structure of the present invention includes a chip package 1 and two pins 2 and 3, wherein the chip package 1 includes a transistor die 11 and a molding compound 12 encapsulating the transistor die 11; and the pin 2 is electrically connected to a first bonding pad 111 and a second bonding pad 112 of the transistor die 11, and the pin 3 is electrically connected to a third bonding pad 113 of the transistor die 11.

[0055]The transistor die 11 of the transistor structure of the present invention is a Bipolar Junction Transistor (BJT) die, and the BJT may be an NPN type BJT die or a PNP type BJT die. Please refer to FIG. 1 in conjunction with FIG. 2A and FIG. 2B. The first bonding pad 111 of the transistor die 11 is an emitter bonding pad, and the second bonding pad 112 is a base bonding pad, and the third bonding pad 113 is a collector bonding pad, whe...

second embodiment

[0061]Please refer to FIG. 1B, which is a diagram illustrating a transistor structure according to the present invention. The transistor structure of the present invention includes a chip package 1 and two pins 2 and 3, wherein the chip package 1 includes a transistor die 11, a capacitor die 13, and a molding compound 12 encapsulating the transistor die 11 and the capacitor die 13. The third bonding pad 113 of the transistor die 11 is electrically connected to a first bonding pad 131 of the capacitor die 13. The pin 2 is electrically connected to a first bonding pad 111 and the second bonding pad 112 of the transistor die 11, and the pin 3 is electrically connected to a second bonding pad 132 of the capacitor die 13. The transistor structure of this embodiment may make the first bonding pad 111 (or the second bond 112) of the transistor die 11 electrically connected to the first bonding pad 131 of the capacitor die 13, may make the pin 2 electrically connected to the second bonding ...

third embodiment

[0064]Please refer to FIG. 1C, which is a diagram illustrating the transistor structure according to the present invention. The transistor structure of the present invention includes a chip package 1 and two pins 2 and 3, wherein the chip package 1 includes a transistor die 11, a capacitor die 13, a zener diode die 14, and a molding compound 12 encapsulating the transistor die 11, the capacitor die 13, and the zener diode die 14. The third bonding pad 113 of the transistor die 11 is electrically connected to a first bonding pad 131 of the capacitor die 13 and a first bonding pad 141 of the zener diode die 14. The pin 2 is electrically connected to a first bonding pad 111 and the second bonding pad 112 of the transistor die 11, and the pin 3 is electrically connected to a second bonding pad 132 of the capacitor die 13 and a second bonding pad 142 of the zener diode die 14. The transistor structure of this embodiment may make the first bonding pad 111 and the second bonding pad 112 of...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A transistor structure includes a chip package and two pins, wherein the chip package includes a transistor die and a molding compound encapsulating the transistor die. One of the pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and another of the pins is electrically connected to a third bonding pad of the transistor die. The transistor structure may be employed in a snubber circuit to connect an active component or a load in parallel to absorb spikes or noise generated by the active component while the active component is switching at a high frequency. Therefore, the packaging of the transistor structure could simplify the process, reduce size, increase the withstanding voltage, and improve the efficiency and reduce the spike voltage of the power supply of the snubber circuit.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of U.S. provisional application No. 61 / 533,796 (filed on Sep. 13, 2011) and U.S. provisional application No. 61 / 682,319 (filed on Aug. 13, 2012). The entire contents of the related applications are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a transistor structure and transistor packaging method thereof, and more particularly, to a transistor structure with two pins and related packaging method thereof.[0004]2. Description of the Prior Art[0005]In recent years, due to the continued development of the technology of electronic circuits, the protection circuits of a variety of electrical / electronic components are widely implemented in many applications. In conventional protection circuits, for instance, a RCD snubber circuit 400 as shown in FIG. 19 is formed by making the resister R6 and the capacitor C12 connected in par...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/498H01L21/56
CPCH01L21/56H01L2924/1305H01L23/62H01L25/16H01L2924/13091H01L2224/16245H01L2224/32245H01L2224/48247H01L2224/73265H01L2224/45144H01L2924/1301H01L2924/1306H01L23/498H01L2224/0401H01L2924/3011H01L23/49562H01L23/4952H01L23/3107H01L2224/49113H01L2224/49107H01L2224/4813H01L2224/48091H01L2224/29339H01L2224/0603H01L24/73H01L2224/16106H01L24/13H01L24/14H01L24/16H01L2224/13111H01L2224/1403H01L2224/14051H01L2924/13055H01L2224/32013H01L24/06H01L24/29H01L24/32H01L24/45H01L24/48H01L24/49H01L2924/00014H01L2924/00012H01L2924/00H01L2924/181H01L2924/12035
Inventor LIN, KUO-FANLIN, CHI-SHANG
Owner SPI ELECTRONICS
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com