Circuits and methods for fault testing

Abstract

An integrated circuit sensor includes circuitry and methods for generating a high speed delay fault test clock signal. A trimmable oscillator generates a master clock signal for use by an output protocol processor to provide the sensor output signal. A fault test clock signal generator is responsive to the master clock signal and to a test trigger signal for generating the test clock signal having a launch pulse and a capture pulse, each having edges substantially coincident with like edges of pulses of the master clock signal and a spacing between launch and capture pulses established by the trimmable master clock signal.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]Not Applicable.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH[0002]Not Applicable.FIELD OF THE INVENTION[0003]This invention relates generally to electronic circuits and, more particularly, to circuits and methods for delay fault testing.BACKGROUND OF THE INVENTION[0004]As digital semiconductor Integrated Circuit (IC) geometries become smaller and signal speeds become faster, fault testing becomes more challenging. Various fault conditions such as marginal contacts, marginal vias, and marginal interconnects can cause signal delay faults.[0005]Automatic Test Equipment (ATE) is used to generate test signals to exercise the digital IC and the resulting IC generated signals may be analyzed by the ATE and / or another external controller. An interface board, sometimes referred to as a Device Under Test (DUT) interface, is generally needed to adapt the ATE generated test signals to a particular IC. The ATE generated test signals generally inclu...

AI Technical Summary

Benefits of technology

The patent describes a way to accurately test delay faults in ICs without needing expensive and complex equipment. This is done by generating a high-speed test clock signal on the chip using an existing oscillator, which avoids the need for additional circuitry. This technique can be used at both the wafer and packaged level, reducing test costs and complexity.

Problems solved by technology

As digital semiconductor Integrated Circuit (IC) geometries become smaller and signal speeds become faster, fault testing becomes more challenging.

Various fault conditions such as marginal contacts, marginal vias, and marginal interconnects can cause signal delay faults.

While delay fault testing is easiest achieved and therefore predominantly preformed at the wafer level, before the semiconductor wafer is separated for individual IC packaging, certain faults may occur after the IC is packaged.

For example, the process of separating the semiconductor wafer and packaging the individual circuits can itself cause failures.

Device level testing is sometimes performed where applications require; however, such testing even more complex and costly DUT boards than wafer level testing.

However, stuck at fault testing may not be sufficient for certain critical applications.

However, there are difficulties in measuring such close edge spacing without adversely impacting the clock signal itself.

If the launch to capture pulse timing cannot be measured or measured accurately, then the potentiometer may be just adjusted until the DUT consistently passes a test, resulting in the test being run without accurate timing information.

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