Load reduced memory module and memory system including the same

Abstract

A device includes a printed circuit board, a clock connector provided on the printed circuit board and configured to be supplied with a first clock signal, a first register buffer provided on the printed circuit board, coupled to the clock connector and, including a first clock generator that produces a second clock signal in response to the first clock signal, a plurality of data connectors, provided on the printed circuit board, a plurality of memory chips each provided on the printed circuit board and including a first data terminal, and a plurality of second register buffers each provided on the printed circuit board independently of the first register buffer.

Description

RELATED APPLICATIONS[0001]This application is a Continuation application of U.S. patent application Ser. No. 12 / 801,326, filed on Jun. 3, 2010, which, in turn, claims priority to Japanese Patent Application 2009-136649, filed on Jun. 5, 2009.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a memory module and a memory system including the same, and more particularly relates to a Load Reduced memory module and a memory system including the same.[0004]2. Description of Related Art[0005]A memory module such as a DIMM (Dual Inline Memory Module) has a configuration in which a large number of memory chips such as DRAMs (Dynamic Random Access Memories) are mounted on a module printed circuit board (PCB). Such a memory module is inserted in a memory slot provided on a motherboard, thereby a data transfer is performed between a memory controller and the memory module. In recent years, because a system requires a considerable amount of memory c...

AI Technical Summary

Benefits of technology

The present invention improves the performance of a data transfer module by using multiple register buffers and a separate command / address / control register buffer. This reduces the distance between the register buffers and the memory chip, resulting in better signal quality and higher data transfer rates.

Problems solved by technology

In recent years, because a system requires a considerable amount of memory capacity, it is hard to provide the required memory capacity with a single memory module.

However, when a plurality of memory modules are mounted on a motherboard, a load capacity of a data line on the motherboard increases, resulting in a degradation of signal quality.

Although it does not cause a serious problem when a data transfer rate between the memory controller and the memory module is relatively low, it may cause a serious problem that the data transfer cannot be performed in a proper manner due to the degradation of the signal quality when the data transfer rate increases to a certain level.

However, because the AMB employed in the Fully Buffered memory module is a sophisticated chip, which is relatively expensive, it causes a problem that the cost of the memory module considerably increases.

Further, because an interface between the memory controller and the AMB is different from a typical interface between the memory controller and the memory chip in the Fully Buffered memory module, it causes another problem that a conventional memory controller cannot be used as it is.

However, from a result of extensive researches on the Load Reduced memory module by the present inventors, it has been found that, when the data transfer rate is considerably high, simply using a single register buffer is not sufficient to maintain the signal quality on the module PCB.

Images