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Buried word line structure and method of forming the same

a word line and line structure technology, applied in the field of buried word line structure and a method of forming the same, can solve the problem of difficult to effectively form such a structure with the existing process steps

Active Publication Date: 2014-06-12
NAN YA TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach allows for the efficient integration of active and isolation areas, enhancing cell size shrinkage and increasing cell density by creating extremely narrow isolation word line trenches that are deeper than wider active word line trenches, while being compatible with existing process steps.

Problems solved by technology

However, it has been difficult to effectively form such structure with the existing process steps.

Method used

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  • Buried word line structure and method of forming the same
  • Buried word line structure and method of forming the same
  • Buried word line structure and method of forming the same

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Embodiment Construction

[0033]Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0034]FIG. 1A to FIG. 1G are schematic cross-sectional views illustrating a method of forming a buried word line structure.

[0035]Referring to FIG. 1A, a first mask layer 102 and an interlayer 104 are sequentially formed on a substrate 100. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. The first mask layer 102 includes carbon. The examples of the first mask layer 102 include amorphous carbon, carbon-containing oxide, carbon-containing oxynitride, carbon-containing nitride, and all spin-on hard masks. The interlayer 104 includes silicon oxynitride or silicon nitride. The first mask layer 102 and the interlayer 104 can be formed through atmospheric pressure CVD (APCVD)...

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Abstract

A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of Invention[0002]The present invention relates to a semiconductor structure and a method of forming the same, and more generally to a buried word line structure and a method of forming the same.[0003]2. Description of Related Art[0004]Non-volatile memories provide the property of multiple entries, retrievals and erasures of data, and are able to retain the stored information even when the electrical power is off. As a result, non-volatile memories are widely used in personal computers and consumer electronic products.[0005]As the degree of integration of a non-volatile memory is getting higher, the critical dimension of the same is getting smaller. A buried word line structure is often employed in sub-28 nm memory technology or below to meet demands for scaling down the devices.[0006]In order to effectively integrate active areas with isolation areas, for example, in a buried-WL DRAM structure, a portion of buried word lines can serve as ac...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L29/78H01L21/28H10B69/00
CPCH01L21/28017H01L29/7827H01L21/76816H01L23/5283H01L2221/101H10B12/488H10B69/00H01L21/76224
Inventor PARK, INHOHEINECK, LARS
Owner NAN YA TECH
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