Radio frequency peak detection with subthreshold biasing

Abstract

A radio-frequency peak amplitude detection circuit includes a load capacitor, a current source that charges the load capacitor and set the bias current for the field effect transistors, and a pair of field effect transistors. The gates of the field effect transistors are biased at a level below the threshold voltage of the transistors. The transistors are arranged in parallel with the capacitor and are operable to drain the capacitor at a rate determined by a differential input at the gates of the transistors. The voltage across the load capacitor is low-pass filtered and has a voltage level representative of the amplitude of the differential input signal.

Description

BACKGROUND OF THE INVENTION[0001]Communications transceivers may utilize numerous architectures to recover data from a modulated carrier signal. These architectures include coherent demodulation, using either intermediate frequency conversion or direct-conversion receivers. Such receivers typically recover or regenerate the communications carrier signal using a phase-locked loop (PLL) and coherent demodulation. Recently, polar receiver architectures have been proposed that extract the modulation phase components from a received modulated signal without using a carrier recovery circuitry. However, the proposed polar receiver architectures and associated signal processing have deficiencies that result in poor performance and high bit error rates (BER). Accordingly, there is a need for improved polar receiver signal processing and architectures.[0002]Various signal processing architectures often make use of peak detectors to measure the peak level of a radio frequency signal. However, ...

AI Technical Summary

Benefits of technology

The solution achieves low power consumption and improved performance by enabling peak detection at lower signal amplitudes, reducing bit error rates and power consumption in wireless receiver applications.

Problems solved by technology

However, the proposed polar receiver architectures and associated signal processing have deficiencies that result in poor performance and high bit error rates (BER).

However, such detectors frequently require the use of a relatively high signal input level.

However, the use of an amplifier can lead to undesirably high levels of power consumption.

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