Direct memory based ring oscillator (DMRO) for on-chip evaluation of SRAM cell delay and stability

Abstract

A novel and useful direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability. The DMRO circuit uses an unmodified SRAM cell in each delay stage of the oscillator. A small amount of external circuitry is added to allow the ring to oscillate and detect read instability errors. An external frequency counter is the only equipment that is required, as there is no need to obtain an exact delay measurement and use a precise waveform generator. The DMRO circuit monitors the delay and stability of an SRAM cell within its real on-chip operating neighborhood. The advantage provided by the circuit is derived from the fact that measuring the frequency of a ring oscillator is easier than measuring the phase difference of signals or generating signals with precise phase, and delivering such signals to / from the chip. In addition, the DMRO enables monitoring of read stability failures.

Description

FIELD OF THE INVENTION[0001]The present invention relates to the field of semiconductor memory, and more particularly relates to a direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability.BACKGROUND OF THE INVENTION[0002]Evaluation and measurement of the wordline to bitline delay is important in the design and manufacture of semiconductor static random access memory (SRAM) cells. The wordline to bitline delay is a part of the read access path delay in any array memory unit. It is important to properly evaluate the delay in order to determine the length of the critical path. Over estimation of the delay implies a too slow clock frequency, while under estimation may cause logical failures.[0003]Existing methods for measuring this delay are complex, and hence the design of latch-based circuits is typically based on simulations. Testing the stability of cells is typically performed using customized test patterns, but it is ...

AI Technical Summary

Benefits of technology

This patent describes a circuit called the DMRO (also known as a delay-monitoring circuit) that helps evaluate the performance and stability of SRAM cells in real-life situations. This circuit is made up of a ring oscillator and a counter, which can compare multiple versions of the SRAM cell circuit and provide a more accurate estimation of its delay. By measuring the frequency of the ring oscillator, the circuit can monitor cell delay and instability, and can also be used as a built-in self-test (BIST) circuit for on-chip testing of SRAM cell behavior. The precision of delay evaluation is not dependent on the on-chip delay lines or counters, which makes it easier to compare different versions of the SRAM cell circuit and make informed decisions about its performance.

Problems solved by technology

Over estimation of the delay implies a too slow clock frequency, while under estimation may cause logical failures.

Existing methods for measuring this delay are complex, and hence the design of latch-based circuits is typically based on simulations.

Testing the stability of cells is typically performed using customized test patterns, but it is difficult to interpret failures, as numerous other factors are at play.

Thus, it has been difficult to measure on-chip wordline to bitline delay due to: (1) the difficulty in producing a precise delay at high frequencies; and (2) the difficulty in delivering the phases of clock and data to the SRAM cell within a chip because the probe / pad / line / connector delay is very complex to control and predict.

This technique requires costly equipment and is difficult to do in practice.

This requires the significant addition of circuitry to the layout, thus costing precious chip real estate.

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