SiGe P-CHANNEL TRI-GATE TRANSISTOR BASED ON BULK SILICON AND FABRICATION METHOD THEREOF

Abstract

A p-channel tri-gate transistor has a silicon fin that protrudes from a bulk silicon substrate, a thin silicon-germanium active layer is formed on three sidewalls of the silicon fin, and a hole well is formed between the gate insulating film and the silicon fin in the active layer surrounded by the tri-gate by a valence band offset electric potential against the silicon fin for moving holes collected in the hole well along the active layer with a high hole-mobility. Thus, it is possible to have the effects of not only an ultra-high speed, low power operation, but also a body biasing through an integral structure of the silicon fin-body. The p-channel tri-gate transistor can be fabricated together with an n-channel FinFET transistor in one substrate by the same CMOS process.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims priority to Korean Patent Application No. 10-2016-0102082, filed on Aug. 11, 2016, under 35 U.S.C. 119, the entire contents of which are hereby incorporated by reference.BACKGROUND OF INVENTION1. Field of the Invention[0002]The present invention relates to a semiconductor transistor, and more particularly to a SiGe p-channel tri-gate transistor based on a bulk silicon and fabrication method thereof.2. Description of the Related Art[0003]CMOS used as the various digital integrated circuits is fabricated by a complementary combination of n-channel and p-channel MOSFETs. The n-channel MOSFET has been widely studied, but the p-channel MOSFET has not.[0004]For an example, an n-channel FinFET structure having a silicon channel with a fin shape protruded from a silicon substrate has been already developed and commercialized, but a p-channel MOSFET improved in performance has not.[0005]Therefore, there has been a problem th...

AI Technical Summary

Benefits of technology

The present invention provides a method to fabricate a SiGe p-channel tri-gate transistor on a bulk silicon substrate. This transistor can be integrated with an n-channel transistor using the same CMOS process. The transistor has a thin silicon-germanium active layer on three sidewalls of a silicon fin, which has a high hole-mobility. The transistor also has a hole well controlled by the tri-gate, which allows for an ultra-high speed, low power operation. The same fabrication method can be used with an n-channel FinFET transistor. The invention solves the problem of inefficient body biasing and provides an integrated structure for the silicon fin-body.

Problems solved by technology

For an example, an n-channel FinFET structure having a silicon channel with a fin shape protruded from a silicon substrate has been already developed and commercialized, but a p-channel MOSFET improved in performance has not.

Therefore, there has been a problem that it is difficult to produce CMOS together with the n-channel and p-channel MOSFETs having the same silicon fin body structure and the same level of a current operating capacity on one bulk silicon substrate by the same process.

However, as mentioned in the prior patent, the tensile strain of the silicon capping layer is merely able to be expected to enhance the electron mobility, but not expected to improve the hole-mobility for a p-channel MOSFET.

Thus, there has been a problem that it is difficult to embody a p-channel MOSFET together with an n-channel MOSFET using the above structure.

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