Laterally diffused field effect transistor and a method of manufacturing the same

Abstract

An LDFET may be formed on the basis of manufacturing platforms designed for forming sophisticated small signal transistor elements. To this end, sidewall areas of trench isolation regions laterally positioned within the drift region may be used as current paths, thereby achieving increased design flexibility, since efficient current paths may still be established, even if the trench isolation regions have to extend into the substrate material due to design criteria determined by the sophisticated small signal transistor elements. In some illustrative embodiments, isolation of P-LDFETs with respect to the P-substrate may be accomplished without requiring a deep well implantation.

Description

BACKGROUND1. Field of the Disclosure[0001]Generally, the present disclosure relates to semiconductor devices and manufacturing techniques in which laterally diffused field effect transistors may be formed on the basis of a manufacturing platform in which sophisticated small transistor elements also have to be implemented.2. Description of the Related Art[0002]Significant progress has been made over the past decades in the field of semiconductor devices by steadily reducing the lateral dimensions of the circuit elements, such as transistor elements, resistors, capacitors and the like. Although various approaches have been taken to form semiconductor devices of ever increasing performance and reduced dimensions, the CMOS technology has been proven to be a most viable candidate and has developed into a technical domain for producing powerful, yet cost effective, semiconductor devices. That is, in the CMOS technology, complementary transistor elements are provided, i.e., P-type transist...

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Benefits of technology

[0009]The present disclosure is generally based on the concept that, even for highly scaled device dimensions, well regions having a profile and depth complying with requirements of sophisticated logic or small signal transistor elements may be used without additional deep dopant implantations, while still providing the required isolation of the drain region of high power / high voltage transistor elements, also referred to as LD (laterally diffused) field effect transistors. To this end, one or more current paths may be implemented in the drift region of the corresponding transistor elements on the basis of one or more trench isolation regions, irrespective of the penetration depth of the trench isolation regions. Consequently, even if design constraints for small signal transistor elements may require an extension of respective trench isolation regions into, or even beyond, the deepest isolating well region, a reliable current path is available near and around the respective sidewall portions of the trench isolation region. Based on this concept, a plurality of design features may be provided so as to further enhance overall performance of the LDFET element.

[0010]One illustrative embodiment disclosed herein relates to a laterally diffused field effect transistor. The laterally diffused field effect transistor comprises a first well region having a first conductivity type, wherein the first well region is formed above a substrate having the first conductivity type. Furthermore, the laterally diffused field effect transistor comprises a drain region having the first conductivity type, which is formed within the first well region. Moreover, a second well region is provided that has a second conductivity type and is formed within the first well region. Additionally, the laterally diffused field effect transistor comprises a source region having the first conductivity type, which is formed within the second well region. Additionally, the laterally diffused field effect transistor comprises a trench isolation region that extends in a depth direction through the first well region and at least into the second well region, wherein the trench isolation region has a width dimension that is less than a width dimension of the first well region so as to form a space region for enabling current flow adjacent to sidewalls of the trench isolation region.

[0011]According to another illustrative embodiment disclosed herein, a laterally diffused field effect transistor is provided. The laterally diffused field effect transistor comprises a first well region having a first conductivity type formed above a substrate having the first conductivity type. Moreover, a drain region is provided that has the first conductivity type and is formed within the first well region and has a first width dimension. Additionally, a second well region having a second conductivity type is formed within the first well region. A trench isolation region is laterally positioned in the first well region and has a second width dimension. Moreover, the laterally diffused field effect transistor comprises a source region having the first conductivity type, wherein the source region is formed in the second well region and has a third width dimension. The third width dimension is greater than the second width dimension, which, in turn, is greater than the first width dimension.

[0012]A still further illustrative embodiment disclosed herein relates to a method. The method includes forming a first well region of a first conductivity type in a device region of a semiconductor device. The method further includes forming a second well region of a second conductivity type below and laterally adjacent to the first well region. Additionally, the method includes forming a laterally diffused field effect transistor in the device region, wherein a drain region of the laterally diffused field effect transistor has the first conductivity type and is positioned in the first well region. Moreover, the second well region isolates the drain region from a substrate that has the first conductivity type.

Problems solved by technology

Consequently, increasingly highly complex control circuitry may have to be combined with analog circuit portions, high power or high voltage circuit portions, RF (radio frequency) circuit elements and the like in order to comply with the various requirements of complex electronic systems.

These small signal transistor elements may provide powerful control circuitry, including a large number of individual transistors, for example, up to several hundred million transistor elements, thereby requiring highly complex manufacturing techniques and process strategies.

Upon further scaling the dimensions of logic transistor elements, for example, requiring a gate length in planar transistor architectures of 30 nm and significantly less, it turns out, however, that, in particular, the requirement for deep well regions in LDFETs may contribute to process-related issues, since, in particular, deep N-well regions may be required to appropriately isolate the drain region of a P-LDFET from the typically P-doped substrate material.

Therefore, additional and complex processes may have to be implemented, thereby contributing to overall process complexity and, thus, manufacturing costs.

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