MASKLESS EPITAXIAL GROWTH OF PHOSPHORUS-DOPED Si AND BORON-DOPED SiGe (Ge) FOR ADVANCED SOURCE/DRAIN CONTACT

Abstract

A method is presented for forming a transistor having reduced parasitic contact resistance. The method includes forming a first device over a semiconductor structure, forming a second device adjacent the first device, forming an ILD over the first and second devices, and forming recesses within the ILD to expose the source / drain regions of the first device and the source / drain regions of the second device. The method further includes forming a first dielectric layer over the ILD and the top surfaces of the source / drain regions of the first and second devices, a chemical interaction between the first dielectric layer and the source / drain regions of the second device resulting in second dielectric layers formed over the source / drain regions of the second device, and forming an epitaxial layer over the source / drain regions of the first device after removing remaining portions of the first dielectric layer.

Description

BACKGROUNDTechnical Field[0001]The present invention relates generally to semiconductor devices, and more specifically, to enabling maskless epitaxial growth of phosphorous-doped silicon (Si:P) and boron-doped silicon-germanium (SiGe:B) for advanced source / drain contact.Description of the Related Art[0002]In 7 nm node technology and beyond, contact resistivity of less than 2e−9 Ω·cm2 is desired for both an n-type field effect transistor (nFET) and a p-type field effect transistor (pFET). A conventional metal liner contact generally has contact resistivity of greater than 1e−8 Ω·cm2 for either the nFET or the pFET due to contact reactive ion etch (RIE) damage and residue at the bottom of the contact trench. The trench epitaxial growth (silicon phosphorous (Si:P) for nFET, germanium (Ge) for pFET) can resolve such issues because metal on Ge has an intrinsically very low Schottky barrier height due to metal Fermi level pinning to the valance band of Ge. Ge epitaxial layer growth within...

AI Technical Summary

Benefits of technology

This approach significantly reduces parasitic contact resistance and process complexity by integrating superior contact properties of germanium with silicon and SiGe, achieving low resistance contacts suitable for advanced transistor configurations.

Problems solved by technology

However, the trench epitaxial growth can be complicated to integrate with the current complementary metal oxide semiconductor (CMOS) process, as it requires more masks and patterning process.

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