Three-dimensional stacked phase change memory and preparation method thereof

Abstract

A three-dimensional stacked phase change memory and a preparation method thereof are provided. The method comprises: preparing first horizontal electrodes spaced apart from each other on a substrate; preparing first strip-shaped phase change layers, each having a central gap, between the first horizontal electrodes; preparing first selectors in the central gaps of the first strip-shaped phase change layers; preparing a first insulating layer; preparing second strip-shaped phase change layers at same vertical positions on the first insulating layer; preparing second selectors; then preparing horizontally-oriented insulating holes between the horizontal electrodes; and preparing vertical electrodes between the adjacent insulating holes, thereby forming a multilayer stacked phase change memory with a vertical structure.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application is a 371 application of the International PCT application serial no. PCT / CN2018 / 118146, filed on Nov. 29, 2018, which claims the priority benefit of China application no. 2018110847703, filed on Sep. 18, 2018. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.BACKGROUNDTechnical Field[0002]The disclosure belongs to the technical field of microelectronic devices and memories, and more particularly relates to a three-dimensional stacked phase change memory and a preparation method thereof.Description of the Related Art[0003]As a new type of memory that is most likely to become one of the mainstream memories in the future, the phase change memory has gradually evolved into three dimensions to meet the demand for high-capacity storage in the era of big data, forming a multi-layer stacked phase change memory.[0004]At present, the thre...

AI Technical Summary

Benefits of technology

The present patent aims to provide a vertical electrode structure for a three-dimensional stacked phase change memory and a preparation method. Compared to existing methods, the present disclosure improves the overall process design of the key preparation method by simplifying the preparation process by effectively handling issues such as complicated steps for multi-layer stacking and scaling down of unit size. The size of the phase change unit is determined by the film thickness, resulting in a higher storage density and reduced operating current and power consumption. The cross structure of horizontal and vertical electrodes allows for the preparation of a large-capacity memory array with a small feature size and a relatively flat surface.

Problems solved by technology

Although this structure is simple, with the increase of the number of stacked layers, the process steps are cumbersome, and the surface unevenness is intensified, bringing about the reliability problem.

In addition, the feature size of the memory cell is limited by advanced photoetching processes, which are costly.

Overall, it is not conducive to further multi-layer stacking and high-density integration.

However, the number of times of photoetching operations is proportional to the number of the three-dimensional stacked layers, the cost of the photoetching process is increased sharply during the multi-layer stacking, and the preparation of each layer of electrodes causes a certain surface unevenness, leading to the serious device reliability problem in multi-layer stacking.

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