3D semiconductor device and structure

Abstract

A 3D semiconductor device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer which includes second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provide first connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the third layer includes crystalline silicon, and where the second level includes at least one scan-chain to support circuit test.

Description

[0001]This application is a continuation-in-part of U.S. patent application Ser. No. 17 / 169,432 filed on Feb. 6, 2021; which is a continuation-in-part of U.S. patent application Ser. No. 17 / 065,424 filed on Oct. 7, 2020 (now U.S. Pat. No. 10,950,581, issued on Mar. 16, 2021); which is a continuation-in-part of U.S. patent application Ser. No. 15 / 482,787 filed on Apr. 9, 2017 (now U.S. Pat. No. 10,840,239, issued on Nov. 17, 2020); which is a continuation-in-part of U.S. patent application Ser. No. 14 / 607,077 filed on Jan. 28, 2015 (now U.S. Pat. No. 9,640,531, issued on May 2, 2017); which claims benefit of provisional U.S. Patent Application No. 62 / 042,229, filed on Aug. 26, 2014, provisional U.S. Patent Application No. 62 / 035,565, filed on Aug. 11, 2014, provisional U.S. Patent Application No. 62 / 022,498, filed on Jul. 9, 2014, and provisional U.S. Patent Application No. 61 / 932,617, filed on Jan. 28, 2014. U.S. patent application Ser. No. 14 / 607,077 is also a continuation-in-part ...

AI Technical Summary

Benefits of technology

This approach effectively manages heat dissipation and prevents damage to metal interconnect layers during annealing, enabling defect-free crystalline semiconductor layers at lower temperatures and improving the yield and reliability of 3D IC devices.

Problems solved by technology

However, wires (interconnects) that connect together transistors degrade in performance with “scaling”.

But this exfoliating implant method can destroy lattice structure of the doped layer 400 by heavy ion-implanting.

In this case, to recover the destroyed lattice structure, a long time thermal treatment in very high temperature is required.

This method has a critical disadvantage which can destroy lattice structures of the substrate because it uses high amount of ion implantation.

However, it is not designed for 3D IC either.

Such high temperature processing certainly destroys underlying devices and interconnect layers.

It seems that there is no way to cure the lattice damage at low temperatures.

BeSang has disruptive 3D layer formation technology and it enables formation of defect-free single crystalline semiconductor layer at low temperatures .

Regardless of the technique used to construct 3D stacked integrated circuits or chips, heat removal is a serious issue for this technology.

Removing the heat produced due to this power density is a significant challenge.

In addition, many heat producing regions in 3D stacked integrated circuits or chips have a high thermal resistance to the heat sink, and this makes heat removal even more difficult.

In addition, thermal limitations during IC fabrication have been a big obstacle on the road to monolithic three-dimensional ICs.

Images