Method and apparatus for performing access management of memory device in host performance booster architecture with aid of device side table information
a memory device and host performance booster technology, applied in the field of memory control, can solve the problems of complex management of accessing flash memory, insufficient storage capacity of the ram, and introduction of further problems, so as to improve the reading prevent some security issues, and enhance the performance of the memory device
Active Publication Date: 2022-02-17
SILICON MOTION INC (TW)
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Benefits of technology
This patent describes a method and apparatus for accessing a memory device in a way that improves performance. The method involves using device side table information to manage access to the memory device. The apparatus includes the memory device and a controller, and can be included in electronic devices like mobile phones or computers. The memory device can store data for the host device and then provide it to the host device when requested. The apparatus can also detect and prevent malfunctions or unauthorized access to the memory device. Overall, this technology ensures the memory device operates properly and improves overall performance.
Problems solved by technology
A memory device may comprise Flash memory for storing data, and the management of accessing the Flash memory is complicated.
The storage capacity of the RAM is typically insufficient.
The related art tries to correct the problem, but further problems are introduced.
Method used
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Embodiment Construction
[0031]FIG. 1 is a diagram of an electronic device 10 according to an embodiment of the present invention, where the electronic device 10 may comprise a host device 50 and a memory device 100. The host device 50 may comprise at least one processor (e.g. one or more processors) which may be collectively referred to as the processor 52, a power supply circuit 54, and at least one random access memory (RAM) (e.g. one or more RAMs, such as a dynamic RAM (DRAM), a static RAM (SRAM), etc.) which may be collectively referred to as the RAM 56), where the processor 52 and the RAM 56 may be coupled to each other through a bus, and may be coupled to the power supply circuit 54 to obtain power. The processor 52 may be arranged to control operations of the host device 50, the power supply circuit 54 may be arranged to provide the processor 52, the RAM 56, and the memory device 100 with power, and output one or more driving voltages to the memory device 100, where the memory device 100 may provide...
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A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information are provided. The method may include: sending internal information of the memory device to a host device, to allow the host device to store the internal information of the memory device in a memory within the host device as host side table information at the host device; generating and storing multiple entries of at least one address mapping control table into a random access memory (RAM) as at least one portion of device side table information at the memory device; determining at least two physical addresses associated with at least two logical addresses according to the at least one address mapping control table; and reading data from the NV memory according to the at least two physical addresses.
Description
CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of U.S. Provisional Application No. 63 / 064,379, which was filed on Aug. 11, 2020, and is included herein by reference.BACKGROUND OF THE INVENTION1. Field of the Invention[0002]The present invention is related to memory control, and more particularly, to a method for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information, and associated apparatus such as the memory device, a controller thereof, an electronic device comprising the memory device, etc.2. Description of the Prior Art[0003]A memory device may comprise Flash memory for storing data, and the management of accessing the Flash memory is complicated. The memory device may comprise a RAM for purposes of buffering, management, etc. The storage capacity of the RAM is typically insufficient. The related art tries to correct the problem, but further problems are introdu...
Claims
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IPC IPC(8): G06F3/06
CPCG06F3/0622G06F3/0679G06F3/0655G06F13/1673G06F3/061G06F3/064
Inventor CHEN, YU-TA
Owner SILICON MOTION INC (TW)