Transistor with reduced gate resistance and improved process margin of forming self-aligned contact

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes two gate structures, a first conductor, a barrier, a second conductor and a plurality of air gaps. The two gate structures are located on a surface of a semiconductor material substrate. The first conductor is disposed between the two gates structures. The barrier is disposed between the first conductor and the gate structure. The second conductor is disposed on the first conductor. The air gaps are disposed at two sides of the second conductor. A width of the second conductor is greater than a width of the first conductor.

Description

TECHNICAL FIELD[0001]The present disclosure relates to a semiconductor structure and a method of forming the same, and more particularly, to a semiconductor structure including at least one functional gate structure having reduced gate resistance and a self-aligned dielectric cap that is designed to increase process margin for self-aligned contact formation, and further a bit line is disposed above the self-aligned dielectric cap and electrically connected to a source-drain region through a bit line contact.DISCUSSION OF THE BACKGROUND[0002]The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size (e.g., shrinking the semiconductor process node towards the sub-20 nm node), which allows more components to be integrated ...

AI Technical Summary

Benefits of technology

[0026]Due to the design of the semiconductor device of the present disclosure, the first conductor and the second conductor are formed to prevent the erosion of the self-aligned dielectric cap corner. In addition, it may prevent source / drain contact which can lead to source / drain contact structure to conductive material shorts and dielectric breakdown (i.e., reliability) issues. A thick self-aligned dielectric cap which may be kept by the first conductor and the second conductor also means deep conductive material recess, which reduces the conductive material volume and thus increases gate resistance.

Problems solved by technology

As a result, the self-aligned dielectric cap has to be thick enough to prevent source / drain contact which can lead to source / drain contact structure to conductive material shorts and dielectric breakdown (i.e., reliability) issues.

In addition, it may prevent source / drain contact which can lead to source / drain contact structure to conductive material shorts and dielectric breakdown (i.e., reliability) issues.

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