Phase lock detection circuit for phase-locked loop circuit

Abstract

The present invention relates to a phase-locked loop (PLL) circuit and, more particularly to a PLL with a phase lock detection circuit. The PLL circuit includes a phase detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a frequency divider, and a phase lock detection circuit having two current charging / discharging circuits with first and second constant current sources for generating a phase lock signal having a pulse form through charging / discharging a capacitor. A voltage level of the capacitor is changed with a hysteresis characteristic. In the out-of-lock state of the PLL circuit, the discharging speed of the capacitor is faster than the charging speed thereof. In the phase lock state of the PLL circuit, the charging speed of the capacitor is faster than the discharging speed thereof. Since the charging / discharging operation of the capacitor is executed linearly and symmetrically, the phase lock detection circuit according to the present invention can obtain stable phase lock information. In addition, it is able to forecast the result of the phase lock state apart from a process variation by using the current mirror.

Description

FIELD OF THE INVENTIONThe present invention relates to a phase-locked loop (PLL) circuit and, more particularly, to a PLL with a phase lock detection circuit.BACKGROUND OF THE INVENTIONPhase-locked loops (PLLs) are found in a myriad of electronic applications such as communication receivers and clock synchronization circuits for computer systems. A conventional PLL includes a phase detector for monitoring the phase difference between an input signal and an output signal of a voltage controlled oscillator (VCO) and generating an up control signal and a down control signal for a charge pump circuit which charges and discharges the loop filter at the input of the VCO. The up and down control signals drive the VCO to maintain a predetermined phase relationship between the signals applied to a phase detector, as is well understood.It is common for the PLL to lose phase lock should the input signal fade or jump to a radically different frequency of operation. The out-of-lock state can be ...

AI Technical Summary

Benefits of technology

To attain the above and other objects, according to an aspect of the present invention there is provided a phase lock detection circuit including: a capacitor; a first constant current source for supplying a first constant current; a second constant current source for supplying a second constant current corresponding to M-times (M is an integer of two and more) the first constant current; a window signal generating circuit responsive to the output signal, for generating a window signal which has a pulse width corresponding to an acceptable phase error; a delay circuit for delaying the input signal; a detection circuit for detecting whether the delayed input signal is within the pulse width of the window signal or not and generating a detection signal as a detection result; a first circuit for supplying the first constant current as

Problems solved by technology

Unfortunately, the pulse widths of the up and down control signals are subject to temperature and process variation and therefore are not well suited as control parameters for ascertaining phase lock.

The pulse widths of the up and down control signals are merely rough indicators having limited accuracy of the true phase relationship between the input signals of the phase detector.

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